公开(公告)号：US20140217532A1

公开(公告)日：2014-08-07

申请号：US14246165

申请日：2014-04-07

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation.

Abstract translation: 形成磁性隧道结（MTJ）装置的方法包括在MTJ结构上形成第一MTJ盖层。 第一MTJ盖层包括第一非硝化金属。 该方法还包括在第一MTJ盖层上形成第二MTJ盖层。 第二MTJ盖层包括第二非硝化金属。 该方法还包括在第二MTJ盖层上形成顶部电极层。 第二MTJ盖层是导电的并且被配置为减少或防止氧化。

公开(公告)号：US20140147941A1

公开(公告)日：2014-05-29

申请号：US14172208

申请日：2014-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: H01L43/12

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

Abstract translation: 半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁隧道结（MTJ）存储元件。 盖层将公共IMD层与顶部和底部IMD层分开。 顶部和底部电极耦合到MTJ存储元件。 金属与电极的连接分别通过分离盖层中的通孔形成在顶部和底部IMD层中。 或者，分离盖层是凹进的并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。 通过用金属岛和隔离帽隔离与MTJ存储元件的金属连接来实现与公共IMD层中顶部电极的金属连接。

公开(公告)号：US20140038312A1

公开(公告)日：2014-02-06

申请号：US14048918

申请日：2013-10-08

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/02

CPC classification number: H01L43/02 ,  B82Y25/00 ,  B82Y40/00 ,  G06F17/5068 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/309 ,  H01F41/32 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.

Abstract translation: 公开了一种磁性隧道接合装置及其制造方法。 在特定实施例中，非暂时计算机可读介质包括处理器可执行指令。 当处理器执行时，指令使处理器开始在磁隧道结结构的自由层上沉积封盖材料以形成覆盖层。 所述指令在由所述处理器执行时使所述处理器启动所述封盖材料的第一层的氧化以形成氧化材料的第一氧化层。

公开(公告)号：US20220102266A1

公开(公告)日：2022-03-31

申请号：US17038098

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin Lim ,  Stanley Seungchul Song ,  Foua Vang ,  Seung Hyuk Kang

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods are disclosed. The circuit includes a front side metal line disposed adjacent to a front side of a semiconductor device for providing front side signal routing. The circuit also includes a back side metal line disposed adjacent to a back side of the semiconductor device for providing back side signal routing. In this manner, the back side area of the semiconductor device may be employed for signal routing to conserve area and/or reduce routing complexity. The circuit also includes a back side-front side connection structure that electrically couples the front side metal line to the back side metal line to support signal routing from the back side to the front side of the circuit, or vice versa to provide greater routing flexibility.

公开(公告)号：US10547460B2

公开(公告)日：2020-01-28

申请号：US15356112

申请日：2016-11-18

Applicant: QUALCOMM Incorporated

Inventor： Peiyuan Wang ,  Chando Park ,  Jimmy Jianan Kan ,  Seung Hyuk Kang

IPC: H04L9/32 ,  G06F21/73 ,  H04L9/08

Abstract: Exemplary features pertain to secure communications using Physical Unclonable Function (PUF) devices. Segments of a message to be encrypted are sequentially applied to a PUF device as a series of challenges to obtain a series of responses for generating a sequence of encryption keys, whereby a previous segment of the message is used to obtain a key for encrypting a subsequent segment of the message. The encrypted message is sent to a separate (receiving) device that employs a logical copy of the PUF device for decrypting the message. The logical copy of the PUF may be a lookup table or the like that maps all permissible challenges to corresponding responses for the PUF and may be generated in advance and stored in memory of the receiving device. The data to be encrypted may be further encoded to more fully exercise the PUF to enhance security. Decryption operations are also described.

公开(公告)号：US10460785B1

公开(公告)日：2019-10-29

申请号：US16011866

申请日：2018-06-19

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Chando Park ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/04 ,  G11C11/18 ,  G11C11/02

Abstract: A magnetoresistive random access memory (MRAM) and associated apparatus and methods are described. The MRAM generally includes a heavy metal layer coupled to a source line, and a plurality of bit cells coupled to a word line, a plurality of bit lines, and the heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to the source line, wherein each of the bit cells comprises a magnetic tunnel junction (MTJ) and a transistor, a gate of the transistor being coupled to the word line, and at least one of a source or a drain of the transistor being coupled to the MTJ or at least one of the bit lines.

公开(公告)号：US10424380B1

公开(公告)日：2019-09-24

申请号：US16009351

申请日：2018-06-15

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jianguo Yao ,  Seung Hyuk Kang

IPC: G11C19/00 ,  G11C14/00 ,  H01L27/22 ,  H01L43/02 ,  H04L9/32 ,  G11C11/16 ,  G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells with added passive resistance are disclosed. Added passive resistance can enhance imbalance between transistors in the SRAM bit cell for improved PUF output reproducibility. Enhancing transistor imbalance can more fully skew the SRAM bit cell for increased PUF output reproducibility while still achieving the benefits of output randomness. In one exemplary aspect, added passive resistances in the SRAM bit cell are coupled to a drain of one or more pull-down N-type FETs (NFETs)) in one or more cross-coupled inverters in the SRAM bit cell to enhance imbalance between the inverters. Enhanced imbalance between the inverters increases sensitivity in the output voltage of the SRAM bit cell for a given change in input voltage resulting in greater skew of the SRAM bit cell for increased reproducibility.

公开(公告)号：US10410714B2

公开(公告)日：2019-09-10

申请号：US15709709

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Venkat Rangan ,  Rashid Ahmed Akbar Attar ,  Nicholas Ka Ming Stevens-Yu

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/56 ,  G11C7/10 ,  G11C8/16 ,  G11C11/418

Abstract: Multi-level cell (MLC) static random access memory (SRAM) (MLC SRAM) cells configured to perform multiplication operations are disclosed. In one aspect, an MLC SRAM cell includes SRAM bit cells, wherein data values stored in SRAM bit cells correspond to a multiple-bit value stored in the MLC SRAM cell that serves as first operand in multiplication operation. Voltage applied to read bit line is applied to each SRAM bit cell, wherein the voltage is an analog representation of a multiple-bit value that serves as a second operand in the multiplication operation. For each SRAM bit cell, if a particular binary data value is stored, a current correlating to the voltage of the read bit line is added to a current sum line. A magnitude of current on the current sum line is an analog representation of a multiple-bit product of the first operand multiplied by the second operand.

公开(公告)号：US10347821B2

公开(公告)日：2019-07-09

申请号：US15819993

申请日：2017-11-21

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Junjing Bao ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L23/544 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

Abstract: A method includes patterning a photo resist layer on top of a semiconductor device. The semiconductor device includes a lower portion, a capping layer formed on top of the lower portion, and an optional oxide layer formed on top of the capping layer. The lower portion includes a dielectric material and an interconnect. The method also includes etching portions of the semiconductor device based on the photo resist layer to expose the interconnect. The method further includes depositing a bottom electrode of a resistive memory device on the interconnect. The bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).

公开(公告)号：US10340395B2

公开(公告)日：2019-07-02

申请号：US15583289

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Fabio Alessio Marino ,  Qingqing Liang ,  Francesco Carobolante ,  Seung Hyuk Kang

IPC: H01L29/06 ,  H01L29/93 ,  H01L29/66 ,  H01L29/94 ,  H01L29/36

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor, and techniques for fabricating the same, implemented using a threshold voltage implant region. For example, the semiconductor variable capacitor generally includes a first non-insulative region disposed above a first semiconductor region, a second non-insulative region disposed above the first semiconductor region, and a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region and disposed adjacent to the second non-insulative region. In certain aspects, the semiconductor variable capacitor also includes a control region disposed above the first semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.