公开(公告)号：US10395704B2

公开(公告)日：2019-08-27

申请号：US15853514

申请日：2017-12-22

申请人： Micron Technology, Inc.

发明人： Hyun Yoo Lee ,  Kang-Yong Kim

IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C16/32 ,  G11C16/28 ,  G11C16/08

摘要： Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.

公开(公告)号：US20190139620A1

公开(公告)日：2019-05-09

申请号：US16019254

申请日：2018-06-26

申请人： Micron Technology, Inc.

发明人： Hyun Yoo Lee

IPC分类号： G11C29/50 ,  G11C29/02

摘要： Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

公开(公告)号：US20190066741A1

公开(公告)日：2019-02-28

申请号：US15692993

申请日：2017-08-31

申请人： MICRON TECHNOLOGY, INC.

发明人： Hyun Yoo Lee

IPC分类号： G11C7/22

摘要： Apparatuses and methods for providing active an inactive clock signals are disclosed. An example apparatus includes an input clock buffer and a clock divider circuit. The input clock buffer includes a receiver circuit configured to receive first and second clock signals or first and second constant voltages. The receiver circuit is further configured to provide first and second output signals based on the complementary clock signals or the first and second constant voltages. The first and second clock signals are complementary and the second constant voltage is less than the first constant voltage. The clock divider circuit is configured to receive the first and second output signals and provide multiphase clock signals based on the first and second output signals from the input clock buffer.

公开(公告)号：US10153030B2

公开(公告)日：2018-12-11

申请号：US15590972

申请日：2017-05-09

申请人： Micron Technology, Inc.

发明人： Hyun Yoo Lee ,  Kang-Yong Kim ,  John D. Porter

IPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G11C7/10

摘要： Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

公开(公告)号：US10090026B2

公开(公告)日：2018-10-02

申请号：US15445795

申请日：2017-02-28

申请人： MICRON TECHNOLOGY, INC.

发明人： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC分类号： G11C7/00 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G06F1/12 ,  G11C11/4093 ,  G11C7/10 ,  G11C19/00

摘要： In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.