公开(公告)号：US20230197814A1

公开(公告)日：2023-06-22

申请号：US17554735

申请日：2021-12-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chen Zhang ,  Jingyun Zhang ,  Carl Radens

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/78696 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/82345

Abstract: Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.

公开(公告)号：US20230180640A1

公开(公告)日：2023-06-08

申请号：US17545635

申请日：2021-12-08

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Carl Radens ,  Ruilong Xie ,  Juntao Li

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L45/1253 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1608 ,  H01L27/2481

Abstract: A stacked phase change memory structure having a cross-point architecture is provided. The stacked phase change memory structure includes at least two phase change material element-containing structures stacked one atop the other. Each phase change material element-containing structure of the plurality of phase change material element-containing structures has a cross-point architecture and includes, from bottom to top, at least one bottom electrode, a phase change material element, and a top electrode.

公开(公告)号：US20230125316A1

公开(公告)日：2023-04-27

申请号：US17510703

申请日：2021-10-26

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  JUNTAO LI

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor structure is provided that includes a second nanosheet device of a second conductivity type stacked over a first nanosheet device of a first conductivity type that is different from the second conductivity type. Each of the first and second nanosheet devices includes at least one semiconductor channel material nanosheet. One side of the least one semiconductor channel material nanosheet of both the first and second nanosheet devices contacts a dielectric material, while another side of the least one semiconductor channel material nanosheet of both the first and second nanosheet devices contacts a functional gate-containing liner that extends laterally to connect to a gate contact of each first and second nanosheet device.

公开(公告)号：US20230122498A1

公开(公告)日：2023-04-20

申请号：US17505067

申请日：2021-10-19

Applicant: International Business Machines Corporation

Inventor： JUNTAO LI ,  Ruilong Xie ,  Kangguo Cheng ,  Carl Radens

IPC: H01L45/00 ,  H01L27/24

Abstract: A phase-change memory device includes a bottom electrode; a stack of alternating electrical conductor layers directly contacting a top surface of the bottom electrode; a metal pillar directly contacting a top surface of the stack; a phase change material element directly contacting a top surface of the metal pillar; and a top electrode on the phase change material element, wherein a lateral dimension of the metal pillar is smaller than that of the stack.

公开(公告)号：US20230090521A1

公开(公告)日：2023-03-23

申请号：US17479623

申请日：2021-09-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Carl Radens ,  Lawrence A. Clevenger ,  Daniel James Dechene ,  Hsueh-Chung Chen

IPC: G06F21/16

Abstract: Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.

公开(公告)号：US20220416157A1

公开(公告)日：2022-12-29

申请号：US17449515

申请日：2021-09-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Carl Radens ,  Juntao Li ,  Ruilong Xie ,  Praneet Adusumilli ,  Oscar van der Straten ,  Alexander Reznicek ,  Zuoguang Liu ,  Arthur Gasasira

IPC: H01L45/00

Abstract: A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.

公开(公告)号：US20220302377A1

公开(公告)日：2022-09-22

申请号：US17207798

申请日：2021-03-22

Applicant: International Business Machines Corporation

Inventor： JUNTAO LI ,  Kangguo Cheng ,  Carl Radens ,  Ruilong Xie

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure for a vertical phase change memory cell that includes a bottom electrode on a portion of a semiconductor substrate and a pair of vertical phase change bridge elements that are each on a portion of the bottom electrode. The semiconductor structure for the vertical phase change memory cell includes a dielectric material separating the pair of vertical phase change bridge elements and a top electrode over the pair of vertical phase change bridge elements.

公开(公告)号：US11349001B2

公开(公告)日：2022-05-31

申请号：US16598065

申请日：2019-10-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  Veeraraghavan Basker ,  Juntao Li

IPC: H01L21/8238 ,  H01L27/11 ,  H01L29/417 ,  H01L27/092 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

公开(公告)号：US11322402B2

公开(公告)日：2022-05-03

申请号：US16540497

申请日：2019-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chih-Chao Yang ,  Carl Radens ,  Juntao Li ,  Kangguo Cheng

IPC: H01L21/768 ,  H01L23/522

Abstract: A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.

公开(公告)号：US11152307B2

公开(公告)日：2021-10-19

申请号：US16223832

申请日：2018-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Carl Radens ,  Junli Wang ,  John H. Zhang

IPC: H01L23/535 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/11

Abstract: A semiconductor structure includes a plurality of field effect transistors formed on a substrate including p-type doped field effect transistors (pFETs) and n-type doped field effect transistors (nFETs). A self-aligned buried local interconnect electrically connects a bottom source or drain region of the pFET with an adjacent bottom source or drain region of the nFET. The self-aligned buried local interconnect is serially aligned with and intermediate opposing ends of a gate electrode. Other embodiments include methods for forming the buried local interconnect.