公开(公告)号：US20100121994A1

公开(公告)日：2010-05-13

申请号：US12267646

申请日：2008-11-10

申请人： Kyu-hyoun Kim ,  Paul W. Coteus

发明人： Kyu-hyoun Kim ,  Paul W. Coteus

IPC分类号： G06F3/00 ,  G06F13/28

CPC分类号： G06F13/1684 ,  G11C5/02 ,  G11C5/063 ,  Y02D10/14

摘要： A memory subsystem, array controller, method, and design structure are provided for a stacked memory array. The memory subsystem includes an array controller and at least one memory array. The array controller includes a primary and secondary buffer interface to communicate with a memory controller via a cascade interconnected bus. The array controller also includes an array access controller to process memory access commands received via one of the primary and secondary buffer interfaces. The at least one memory array includes a memory cell array die separately packaged with respect to the array controller and coupled to the array controller in a stacked configuration via memory core data lines using through silicon vias (TSVs).

摘要翻译： 为堆叠的存储器阵列提供存储器子系统，阵列控制器，方法和设计结构。 存储器子系统包括阵列控制器和至少一个存储器阵列。 阵列控制器包括主缓冲器和辅助缓冲器接口，用于经由级联的互连总线与存储器控制器进行通信。 阵列控制器还包括一个阵列访问控制器，用于处理通过主缓冲区和辅助缓冲区接口之一接收的存储器访问命令。 所述至少一个存储器阵列包括相对于阵列控制器单独封装的存储单元阵列，并且经由存储器核心数据线通过硅通孔（TSV）以堆叠配置耦合到阵列控制器。

公开(公告)号：US07683725B2

公开(公告)日：2010-03-23

申请号：US11838282

申请日：2007-08-14

申请人： Kyu-hyoun Kim ,  Paul W. Coteus

发明人： Kyu-hyoun Kim ,  Paul W. Coteus

IPC分类号： H03K3/03

CPC分类号： H03K3/0315 ,  H03K5/15026 ,  H03K5/1506

摘要： A system for generating a multiple phase clock is provided. The system includes a ring oscillator structure for generating multiple phases. The structure includes two or more unit oscillators, each unit oscillator implemented by a ring oscillator having M stages. The structure also includes a horizontal loop coupling the two or more unit oscillators to generate multiple phases. The number of phases generated is equal to the product of the number of unit oscillators and M. Another structure generates multiple phases using a multi-dimensional oscillator including ring oscillators constructed as vertical and horizontal loops with shared elements between the oscillators. A memory system includes a ring oscillator structure with vertical and horizontal loops, the ring oscillator structure receiving an input clock and outputting a multiple phase clock to one or more of a memory controller, memory devices and a memory interface device.

摘要翻译： 提供了一种用于产生多相时钟的系统。 该系统包括用于产生多相的环形振荡器结构。 该结构包括两个或多个单元振荡器，每个单位振荡器由具有M级的环形振荡器实现。 该结构还包括耦合两个或多个单元振荡器以产生多个相位的水平环路。 产生的相数等于单位振荡器和M的数量的乘积。另一种结构使用多维振荡器产生多个相位，该多维振荡器包括环形振荡器，其被构造为在振荡器之间具有共享元件的垂直和水平回路。 存储器系统包括具有垂直和水平环路的环形振荡器结构，环形振荡器结构接收输入时钟并将多相时钟输出到存储器控制器，存储器件和存储器接口器件中的一个或多个。

公开(公告)号：US20090251988A1

公开(公告)日：2009-10-08

申请号：US12061045

申请日：2008-04-02

申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Warren E. Maule ,  Kenneth L. Wright

发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Warren E. Maule ,  Kenneth L. Wright

IPC分类号： G11C8/00

CPC分类号： G11C5/00 ,  G11C7/1018

摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.

摘要翻译： 提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。 存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。 非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。

公开(公告)号：US07593288B2

公开(公告)日：2009-09-22

申请号：US11959711

申请日：2007-12-19

申请人： Kyu-hyoun Kim ,  Paul W. Coteus

发明人： Kyu-hyoun Kim ,  Paul W. Coteus

IPC分类号： G11C7/00

CPC分类号： G11C5/04 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03L7/07 ,  H03L7/0812

摘要： A system for providing read clock sharing between memory devices. The system includes a memory device having an external clock receiver, a read clock receiver, and a phase comparator. The phase comparator synchronizes an internal read clock generated at the memory device. The phase comparator additionally synchronizes one of an external clock received by the external clock receiver and an external read clock received by the read clock receiver. The results of the synchronizing are utilized to refresh the internal read clock. The memory device also includes a mechanism, a read clock driver and a mode register fit. The mechanism is utilized to select between the external clock and the external read clock as input to the phase comparator. The read clock driver outputs the internal read clock generated at the memory device to a read clock output pin. The mode register bit controls the selection of the mechanism, the enabling and disabling of the read clock receiver and the enabling and disabling of the read clock driver.

摘要翻译： 一种用于在存储器件之间提供读时钟共享的系统。 该系统包括具有外部时钟接收器，读取时钟接收器和相位比较器的存储器件。 相位比较器同步存储器件产生的内部读时钟。 相位比较器还将由外部时钟接收器接收到的外部时钟和由读取时钟接收器接收到的外部读取时钟之一进行同步。 利用同步的结果刷新内部读时钟。 存储器件还包括机构，读时钟驱动器和模式寄存器配合。 该机制用于在外部时钟和外部读取时钟之间选择作为相位比较器的输入。 读时钟驱动器将存储器件产生的内部读时钟输出到读时钟输出引脚。 模式寄存器位控制机制的选择，读时钟接收器的使能和禁止以及读时钟驱动器的使能和禁止。

公开(公告)号：US20080285697A1

公开(公告)日：2008-11-20

申请号：US11749409

申请日：2007-05-16

申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Daniel M. Dreps

发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Daniel M. Dreps

IPC分类号： H03D3/24

CPC分类号： H03K5/151 ,  H03K5/13 ,  H03K2005/00052 ,  H03K2005/00234

摘要： A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.

摘要翻译： 一种用于提供开环正交时钟生成的系统。 该系统由环形振荡器结构实现，该环形振荡器结构包括用于接收输入时钟的输入反相器，正向环路逆变器，反向环路逆变器，一个或多个输出以及连接在任何两个相对节点之间的交叉耦合的锁存器。

公开(公告)号：US20070146043A1

公开(公告)日：2007-06-28

申请号：US11679375

申请日：2007-02-27

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03L5/00

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。

公开(公告)号：US20070139093A1

公开(公告)日：2007-06-21

申请号：US11679519

申请日：2007-02-27

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03L5/00

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

公开(公告)号：US07199630B2

公开(公告)日：2007-04-03

申请号：US11158013

申请日：2005-06-21

申请人： Kyu-hyoun Kim

发明人： Kyu-hyoun Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  H03L7/0995

摘要： Delay locked loops include a ring oscillator having serially connected inverters and a feedback path around the serially connected converters. The ring oscillator is configured to generate an output clock signal that is a delayed version of an input clock signal, in response to the input clock signal and to a control signal that is applied to the ring oscillator. A phase responsive circuit is configured to generate the control signal in response to a phase difference between the input clock signal and the output clock signal. Analogous methods of delaying a clock signal also are described.

摘要翻译： 延迟锁定环路包括具有串联连接的反相器的环形振荡器和串联连接的转换器周围的反馈路径。 环形振荡器被配置为响应于输入时钟信号和施加到环形振荡器的控制信号而产生作为输入时钟信号的延迟版本的输出时钟信号。 相位响应电路被配置为响应于输入时钟信号和输出时钟信号之间的相位差而产生控制信号。 还描述了延迟时钟信号的类似方法。

公开(公告)号：US20060076992A1

公开(公告)日：2006-04-13

申请号：US11158013

申请日：2005-06-21

申请人： Kyu-hyoun Kim

发明人： Kyu-hyoun Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  H03L7/0995

摘要： Delay locked loops include a ring oscillator having serially connected inverters and a feedback path around the serially connected converters. The ring oscillator is configured to generate an output clock signal that is a delayed version of an input clock signal, in response to the input clock signal and to a control signal that is applied to the ring oscillator. A phase responsive circuit is configured to generate the control signal in response to a phase difference between the input clock signal and the output clock signal. Analogous methods of delaying a clock signal also are described.

摘要翻译： 延迟锁定环路包括具有串联连接的反相器的环形振荡器和串联连接的转换器周围的反馈路径。 环形振荡器被配置为响应于输入时钟信号和施加到环形振荡器的控制信号而产生作为输入时钟信号的延迟版本的输出时钟信号。 相位响应电路被配置为响应于输入时钟信号和输出时钟信号之间的相位差而产生控制信号。 还描述了延迟时钟信号的类似方法。

公开(公告)号：US06980036B2

公开(公告)日：2005-12-27

申请号：US10671105

申请日：2003-09-25

申请人： Kyoung-hwan Kwon ,  Hyun-soon Jang ,  Kyu-hyoun Kim

发明人： Kyoung-hwan Kwon ,  Hyun-soon Jang ,  Kyu-hyoun Kim

IPC分类号： G06F1/04 ,  G11C11/40 ,  G11C29/00 ,  G11C29/12 ,  H03B1/00 ,  H03B19/00 ,  H03B19/10 ,  H03K5/00 ,  H03K5/1534 ,  H03K21/10

CPC分类号： H03K5/1534 ,  H03K5/00006

摘要： In a frequency multiplier and a method of multiplying a frequency of an external clock signal, a data output buffer, and a semiconductor device including the frequency multiplier and the data output buffer, the frequency multiplier receives an external clock signal having a predetermined frequency and outputs an internal clock signal having greater frequency than the predetermined frequency. In the semiconductor device, the data output buffer outputs data tested in response to test data. Therefore, it is possible to test a plurality of memory cells at a time by using a clock signal having a low frequency. In addition, the time and cost required for the test can be greatly reduced, and conventional testing equipment that operates at a relatively low frequency can be effectively used.

摘要翻译： 在频率倍增器和将外部时钟信号的频率，数据输出缓冲器和包括倍频器和数据输出缓冲器的半导体器件相乘的方法中，倍频器接收具有预定频率的外部时钟信号并输出 具有比预定频率更大的频率的内部时钟信号。 在半导体器件中，数据输出缓冲器输出根据测试数据测试的数据。 因此，可以通过使用具有低频率的时钟信号来一次测试多个存储单元。 此外，可以大大降低测试所需的时间和成本，并且可以有效地使用在较低频率下工作的常规测试设备。