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    Semiconductor device comprising frequency multiplier of external clock and output buffer of test data and semiconductor test method
    1.
    发明授权
    Semiconductor device comprising frequency multiplier of external clock and output buffer of test data and semiconductor test method 失效
    半导体器件包括外部时钟的倍频器和测试数据的输出缓冲器以及半导体测试方法

    公开(公告)号：US06980036B2

    公开(公告)日：2005-12-27

    申请号：US10671105

    申请日：2003-09-25

    申请人： Kyoung-hwan Kwon ,  Hyun-soon Jang ,  Kyu-hyoun Kim

    发明人： Kyoung-hwan Kwon ,  Hyun-soon Jang ,  Kyu-hyoun Kim

    IPC分类号： G06F1/04 ,  G11C11/40 ,  G11C29/00 ,  G11C29/12 ,  H03B1/00 ,  H03B19/00 ,  H03B19/10 ,  H03K5/00 ,  H03K5/1534 ,  H03K21/10

    CPC分类号： H03K5/1534 ,  H03K5/00006

    摘要： In a frequency multiplier and a method of multiplying a frequency of an external clock signal, a data output buffer, and a semiconductor device including the frequency multiplier and the data output buffer, the frequency multiplier receives an external clock signal having a predetermined frequency and outputs an internal clock signal having greater frequency than the predetermined frequency. In the semiconductor device, the data output buffer outputs data tested in response to test data. Therefore, it is possible to test a plurality of memory cells at a time by using a clock signal having a low frequency. In addition, the time and cost required for the test can be greatly reduced, and conventional testing equipment that operates at a relatively low frequency can be effectively used.

    摘要翻译： 在频率倍增器和将外部时钟信号的频率，数据输出缓冲器和包括倍频器和数据输出缓冲器的半导体器件相乘的方法中，倍频器接收具有预定频率的外部时钟信号并输出 具有比预定频率更大的频率的内部时钟信号。 在半导体器件中，数据输出缓冲器输出根据测试数据测试的数据。 因此，可以通过使用具有低频率的时钟信号来一次测试多个存储单元。 此外，可以大大降低测试所需的时间和成本，并且可以有效地使用在较低频率下工作的常规测试设备。

    Semiconductor device with bus line loading compensation circuit
    2.
    发明授权
    Semiconductor device with bus line loading compensation circuit 失效
    具有总线负载补偿电路的半导体器件

    公开(公告)号：US5999031A

    公开(公告)日：1999-12-07

    申请号：US683376

    申请日：1996-07-18

    申请人： Hyun-soon Jang

    发明人： Hyun-soon Jang

    IPC分类号： G11C11/417 ,  G06F3/00 ,  G06F13/16 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0948 ,  H03H11/26

    CPC分类号： H03K19/01721

    摘要： A semiconductor device is provided having an input driver and an output receiver connected by a bus line, the bus line including pulse generating and driver circuitry responsive to threshold levels of voltage change so as to perform high speed switching which compensates for the load of the bus line.

    摘要翻译： 提供了一种半导体器件，其具有通过总线连接的输入驱动器和输出接收器，该总线包括响应阈值电压变化的脉冲产生和驱动器电路，从而执行补偿总线负载的高速切换 线。

    Power down voltage control method and apparatus
    3.
    发明授权
    Power down voltage control method and apparatus 有权

    公开(公告)号：US06510096B2

    公开(公告)日：2003-01-21

    申请号：US09981945

    申请日：2001-10-17

    申请人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

    发明人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

    IPC分类号： G11C802

    CPC分类号： G11C5/143 ,  G11C7/22

    摘要： A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.

    Integrated circuit memory devices having reduced power consumption requirements during standby mode operation
    5.
    发明授权
    Integrated circuit memory devices having reduced power consumption requirements during standby mode operation 有权
    集成电路存储器件在待机模式操作期间具有降低的功耗要求

    公开(公告)号：US6058063A

    公开(公告)日：2000-05-02

    申请号：US187544

    申请日：1998-11-06

    申请人： Hyun-soon Jang

    发明人： Hyun-soon Jang

    IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/413 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/0175 ,  G11C7/00

    CPC分类号： G11C7/1084 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/1078

    摘要： Integrated circuit memory devices (e.g., SDRAM) include an input buffer and a power reduction control circuit which disables the input buffer in response to an inactive chip select signal (CSB). The input buffer comprises a first differential amplifier having a first input electrically coupled to an input signal line (PX) and a first pull-up transistor electrically connected in series between a pull-up reference node of the first differential amplifier and a power supply signal line (e.g., Vcc). The output of the power reduction control circuit is electrically connected to a gate electrode of the first pull-up transistor. The first pull-up transistor can be turned off in response to an inactive chip select signal (CSB=1), to thereby electrically disconnect the first differential amplifier from its power supply. The input buffer may also comprise a first pull-down transistor electrically connected in series between an output of the first differential amplifier and a reference potential signal line (e.g., GND) and the output of the power reduction control circuit is electrically connected to a gate electrode of the first pull-down transistor.

    摘要翻译： 集成电路存储器件（例如，SDRAM）包括输入缓冲器和功率降低控制电路，其响应于非活动芯片选择信号（CSB）禁用输入缓冲器。 输入缓冲器包括具有电耦合到输入信号线（PX）的第一输入的第一差分放大器和串联地电连接在第一差分放大器的上拉参考节点和电源信号之间的第一上拉晶体管 线（例如，Vcc）。 功率降低控制电路的输出电连接到第一上拉晶体管的栅电极。 可以响应于非活动芯片选择信号（CSB = 1）而关断第一上拉晶体管，从而将第一差分放大器与其电源电断开。 输入缓冲器还可以包括串联电连接在第一差分放大器的输出端和参考电位信号线（例如，GND）之间的第一下拉晶体管，并且功率降低控制电路的输出电连接到栅极 第一下拉晶体管的电极。

    Parallel bit test apparatus and parallel bit test method capable of reducing test time
    6.
    发明授权
    Parallel bit test apparatus and parallel bit test method capable of reducing test time 失效
    并行位测试装置和并行位测试方法，能够减少测试时间

    公开(公告)号：US07941714B2

    公开(公告)日：2011-05-10

    申请号：US12003900

    申请日：2008-01-03

    申请人： Yong-hwan Cho ,  Kwun-soo Cheon ,  Hyun-soon Jang ,  Seung-whan Seo

    发明人： Yong-hwan Cho ,  Kwun-soo Cheon ,  Hyun-soon Jang ,  Seung-whan Seo

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/40 ,  G11C5/04 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/2602

    摘要： A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

    摘要翻译： 包含在堆叠在多芯片封装（MCP）中并且共享一组数据信号线的存储器芯片中的并行位测试（PBT）装置可以包括：比较单元，用于输出表示比较的数据信号 分别提供给给定的一个存储器芯片的测试数据信号和从其输出的相应的数据信号之间; 以及编码单元，用于使用所述共享数据信号线组的第一子集输出所述代表数据信号，所述第一子集分别不与由所述存储器芯片中的其他存储器芯片对应的编码单元使用的其他子集重叠，所述编码单元选择 根据第一测试模式寄存器组（MRS）信号将数据信号线的共享数据集中的一个或多个数据信号线包括在第一子集中。

    Parallel bit test apparatus and parallel bit test method capable of reducing test time
    7.
    发明申请
    Parallel bit test apparatus and parallel bit test method capable of reducing test time 失效
    并行位测试装置和并行位测试方法，能够减少测试时间

    公开(公告)号：US20080168316A1

    公开(公告)日：2008-07-10

    申请号：US12003900

    申请日：2008-01-03

    申请人： Yong-hwan Cho ,  Kwun-soo Cheon ,  Hyun-soon Jang ,  Seung-whan Seo

    发明人： Yong-hwan Cho ,  Kwun-soo Cheon ,  Hyun-soon Jang ,  Seung-whan Seo

    IPC分类号： H03M13/00 ,  G06F11/00

    CPC分类号： G11C29/40 ,  G11C5/04 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/2602

    摘要： A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

    摘要翻译： 包含在堆叠在多芯片封装（MCP）中并且共享一组数据信号线的存储器芯片中的并行位测试（PBT）装置可以包括：比较单元，用于输出表示比较的数据信号 分别提供给给定的一个存储器芯片的测试数据信号和从其输出的相应的数据信号之间; 以及编码单元，用于使用所述共享数据信号线组的第一子集输出所述代表数据信号，所述第一子集分别不与由所述存储器芯片中的其他存储器芯片对应的编码单元使用的其他子集重叠，所述编码单元选择 根据第一测试模式寄存器组（MRS）信号将数据信号线的共享数据集中的一个或多个数据信号线包括在第一子集中。

    Power down voltage control method and apparatus
    8.
    发明授权
    Power down voltage control method and apparatus 有权

    公开(公告)号：US06560158B2

    公开(公告)日：2003-05-06

    申请号：US09981782

    申请日：2001-10-17

    申请人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

    发明人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

    IPC分类号： G11C800

    CPC分类号： G11C5/143

    摘要： A semiconductor device is provided for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory comprising; a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and biasing circuitry for biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to prevent false triggering of circuits upon entry/exit of DPD mode. Also provided is a semiconductor device, comprising: a plurality of input buffers for buffering a plurality of DPD-type signals for signaling a power down (DPD) condition including a DPD enter/exit signal: an auxiliary buffer for separately buffering the DPD enter/exit signal; a plurality of voltage generators for supplying operating voltages to internal circuit; DPD control circuit for receiving the DPD-type signals to decode DPD enter and exit commands and for outputting a voltage generator control signal to turn off the voltage generators when DPD enter command is decoded, and to turn off the plurality of buffers excluding the auxiliary buffer; and an auto-pulse generator for generating a voltage pulse upon receiving the DPD exit command to initialize internal circuits of the semiconductor device.

    Sense amplifier of semiconductor integrated circuit
    10.
    发明授权
    Sense amplifier of semiconductor integrated circuit 失效
    半导体集成电路的感应放大器

    公开(公告)号：US06476646B2

    公开(公告)日：2002-11-05

    申请号：US09956577

    申请日：2001-09-18

    申请人： Jae-yoon Sim ,  Hyun-soon Jang ,  Woo-seop Jeong ,  Kyung-ho Kim

    发明人： Jae-yoon Sim ,  Hyun-soon Jang ,  Woo-seop Jeong ,  Kyung-ho Kim

    IPC分类号： G01R1900

    CPC分类号： H03F3/347 ,  G11C7/062 ,  G11C7/065 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/72 ,  H03F2203/45418 ,  H03F2203/45562 ,  H03F2203/45571 ,  H03F2203/45574 ,  H03F2203/45644 ,  H03F2203/45652 ,  H03F2203/45674 ,  H03K5/2481

    摘要： A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and a complement of the input signal. The sense amplifier includes cross-coupled transistors. Each unique cross-coupled transistor is coupled to a corresponding unique transistor formed as a diode. A resistor is coupled in series between one cross-coupled resistor and an input port receiving the input signal, and another resistor is coupled in series between the other cross-coupled transistor and another input port receiving the complement of the input signal. Resistances associated with the sources of each cross-coupled transistor provide the resistance of the resistors.

    摘要翻译： 半导体集成电路包括用于放大输入信号的读出放大器和输入信号的补码。 读出放大器包括交叉耦合晶体管。 每个独特的交叉耦合晶体管耦合到形成为二极管的对应的唯一晶体管。 电阻器串联耦合在一个交叉耦合电阻器和接收输入信号的输入端口之间，另一个电阻器串联耦合在另一个交叉耦合晶体管和另一个输入端口，该输入端口接收输入信号的补码。 与每个交叉耦合晶体管的源极相关的电阻提供了电阻器的电阻。