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    Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit
    1.
    发明授权
    Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit 失效
    具有测试地址产生电路的半导体存储器件和具有测试地址产生电路的半导体存储器件的测试方法

    公开(公告)号：US08051341B2

    公开(公告)日：2011-11-01

    申请号：US12214453

    申请日：2008-06-19

    申请人： Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-II Kim

    发明人： Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-II Kim

    IPC分类号： G11C29/00

    CPC分类号： G11C29/20 ,  G11C2029/3602

    摘要： A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

    摘要翻译： 半导体存储器件包括在该器件上配置的测试地址产生电路。 测试地址产生电路响应于至少一个外部施加的测试地址产生信号，产生用于半导体存储器件测试的多个测试地址。 结果，基于所需地址引脚的减少，DUT的数量可以增加，并且半导体存储器件的制造生产率和测试效率可以增加。

    PERIPHERAL DEVICE INTEGRATED UBIQUITOUS MULTIFUNCTION PERSONAL COMPUTER
    2.
    发明申请
    PERIPHERAL DEVICE INTEGRATED UBIQUITOUS MULTIFUNCTION PERSONAL COMPUTER 审中-公开
    外围设备集成UBIQUITOUS多功能个人计算机

    公开(公告)号：US20080043417A1

    公开(公告)日：2008-02-21

    申请号：US11565863

    申请日：2006-12-01

    申请人： Byong-rok Lee ,  Yong-hwan Cho

    发明人： Byong-rok Lee ,  Yong-hwan Cho

    IPC分类号： G06F1/16

    CPC分类号： G06F1/1605 ,  G06F1/181 ,  G06F2200/1612

    摘要： Disclosed is a peripheral device integrated ubiquitous multifunction PC in which an internet phone device and a PLC modem are integrated. The multifunction PC integrated with a monitor includes a main body including a case provided with basic components and an internet telephone apparatus, and an LCD panel at the front side, and a stand at the lower side of the main body to support the main body. The main body includes a power supply of the case and connected to a power line, a modem provided in the case and including a PLC modem connected to the power supply to modulate/demodulate a signal transmitted through the power line, a telephone receiver provided at a side of the case, and a web-camera provided at the front upper side of the case. The stand includes dial buttons and a key telephone that are provided in the front side thereof.

    摘要翻译： 公开了集成了互联网电话设备和PLC调制解调器的外围设备集成的普遍存在的多功能PC。 与显示器集成的多功能PC包括：主体，包括具有基本部件的壳体和互联网电话设备;以及前侧的LCD面板;以及支撑主体的主体下侧的支架。 主体包括壳体的电源并连接到电力线，设置在壳体中的调制解调器，并且包括连接到电源的PLC调制解调器，以调制/解调通过电力线传输的信号;电话接收器，其设置在 壳体的一侧和设置在壳体的前上侧的网络摄像机。 支架包括在其前侧设置的拨号键和钥匙电话。

    Semiconductor memory device and test system of a semiconductor memory device
    3.
    发明申请
    Semiconductor memory device and test system of a semiconductor memory device 审中-公开
    一种半导体存储器件的半导体存储器件和测试系统

    公开(公告)号：US20090044063A1

    公开(公告)日：2009-02-12

    申请号：US11974342

    申请日：2007-10-12

    申请人： Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

    发明人： Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/2602 ,  G11C2029/5602

    摘要： A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.

    摘要翻译： 半导体存储器件包括存储器核心单元，N个数据输出缓冲器，N个数据输出端口以及多个测试逻辑电路。 存储核心单元通过N条数据线存储测试数据。 N个数据输出缓冲器分别连接到相应的N个数据线。 N个数据输出端口连接到相应的N个数据输出缓冲器，并分别与外部测试仪交换测试数据。 多个测试逻辑电路通过来自N条数据线的K条数据线接收测试数据，对所接收的测试数据进行测试逻辑运算，并提供一个数据输出缓冲器控制信号，该信号确定N个数据输出缓冲器的激活 测试模式下的数据输出缓冲区。 半导体存储器件降低了测试周期。

    Parallel bit test apparatus and parallel bit test method capable of reducing test time
    4.
    发明授权
    Parallel bit test apparatus and parallel bit test method capable of reducing test time 失效
    并行位测试装置和并行位测试方法，能够减少测试时间

    公开(公告)号：US07941714B2

    公开(公告)日：2011-05-10

    申请号：US12003900

    申请日：2008-01-03

    申请人： Yong-hwan Cho ,  Kwun-soo Cheon ,  Hyun-soon Jang ,  Seung-whan Seo

    发明人： Yong-hwan Cho ,  Kwun-soo Cheon ,  Hyun-soon Jang ,  Seung-whan Seo

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/40 ,  G11C5/04 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/2602

    摘要： A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

    摘要翻译： 包含在堆叠在多芯片封装（MCP）中并且共享一组数据信号线的存储器芯片中的并行位测试（PBT）装置可以包括：比较单元，用于输出表示比较的数据信号 分别提供给给定的一个存储器芯片的测试数据信号和从其输出的相应的数据信号之间; 以及编码单元，用于使用所述共享数据信号线组的第一子集输出所述代表数据信号，所述第一子集分别不与由所述存储器芯片中的其他存储器芯片对应的编码单元使用的其他子集重叠，所述编码单元选择 根据第一测试模式寄存器组（MRS）信号将数据信号线的共享数据集中的一个或多个数据信号线包括在第一子集中。

    Semiconductor memory device having test address generating circuit and test method thereof
    5.
    发明申请
    Semiconductor memory device having test address generating circuit and test method thereof 失效
    具有测试地址产生电路的半导体存储器件及其测试方法

    公开(公告)号：US20090006913A1

    公开(公告)日：2009-01-01

    申请号：US12214453

    申请日：2008-06-19

    申请人： Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-Il Kim

    发明人： Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-Il Kim

    IPC分类号： G11C29/04 ,  G06F11/26

    CPC分类号： G11C29/20 ,  G11C2029/3602

    摘要： A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

    摘要翻译： 半导体存储器件包括在该器件上配置的测试地址产生电路。 测试地址产生电路响应于至少一个外部施加的测试地址产生信号，产生用于半导体存储器件测试的多个测试地址。 结果，基于所需地址引脚的减少，DUT的数量可以增加，并且半导体存储器件的制造生产率和测试效率可以增加。

    Parallel bit test apparatus and parallel bit test method capable of reducing test time
    6.
    发明申请
    Parallel bit test apparatus and parallel bit test method capable of reducing test time 失效
    并行位测试装置和并行位测试方法，能够减少测试时间

    公开(公告)号：US20080168316A1

    公开(公告)日：2008-07-10

    申请号：US12003900

    申请日：2008-01-03

    申请人： Yong-hwan Cho ,  Kwun-soo Cheon ,  Hyun-soon Jang ,  Seung-whan Seo

    发明人： Yong-hwan Cho ,  Kwun-soo Cheon ,  Hyun-soon Jang ,  Seung-whan Seo

    IPC分类号： H03M13/00 ,  G06F11/00

    CPC分类号： G11C29/40 ,  G11C5/04 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/2602

    摘要： A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

    摘要翻译： 包含在堆叠在多芯片封装（MCP）中并且共享一组数据信号线的存储器芯片中的并行位测试（PBT）装置可以包括：比较单元，用于输出表示比较的数据信号 分别提供给给定的一个存储器芯片的测试数据信号和从其输出的相应的数据信号之间; 以及编码单元，用于使用所述共享数据信号线组的第一子集输出所述代表数据信号，所述第一子集分别不与由所述存储器芯片中的其他存储器芯片对应的编码单元使用的其他子集重叠，所述编码单元选择 根据第一测试模式寄存器组（MRS）信号将数据信号线的共享数据集中的一个或多个数据信号线包括在第一子集中。