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    Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit
    1.
    发明授权
    Semiconductor memory device having test address generating circuit and method of testing semiconductor memory device having a test address generating circuit 失效
    具有测试地址产生电路的半导体存储器件和具有测试地址产生电路的半导体存储器件的测试方法

    公开(公告)号：US08051341B2

    公开(公告)日：2011-11-01

    申请号：US12214453

    申请日：2008-06-19

    Applicant: Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-II Kim

    Inventor： Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-II Kim

    IPC: G11C29/00

    CPC classification number: G11C29/20 ,  G11C2029/3602

    Abstract: A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

    Abstract translation: 半导体存储器件包括在该器件上配置的测试地址产生电路。 测试地址产生电路响应于至少一个外部施加的测试地址产生信号，产生用于半导体存储器件测试的多个测试地址。 结果，基于所需地址引脚的减少，DUT的数量可以增加，并且半导体存储器件的制造生产率和测试效率可以增加。

    Semiconductor memory device having test address generating circuit and test method thereof
    2.
    发明申请
    Semiconductor memory device having test address generating circuit and test method thereof 失效
    具有测试地址产生电路的半导体存储器件及其测试方法

    公开(公告)号：US20090006913A1

    公开(公告)日：2009-01-01

    申请号：US12214453

    申请日：2008-06-19

    Applicant: Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-Il Kim

    Inventor： Yong-Hwan Cho ,  Hyung-Dong Kim ,  Woo-Il Kim

    IPC: G11C29/04 ,  G06F11/26

    CPC classification number: G11C29/20 ,  G11C2029/3602

    Abstract: A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number of DUTs can increase, based on a reduction of required address pins, and manufacturing productivity and test efficiency of semiconductor memory devices can increase.

    Abstract translation: 半导体存储器件包括在该器件上配置的测试地址产生电路。 测试地址产生电路响应于至少一个外部施加的测试地址产生信号，产生用于半导体存储器件测试的多个测试地址。 结果，基于所需地址引脚的减少，DUT的数量可以增加，并且半导体存储器件的制造生产率和测试效率可以增加。

    Semiconductor memory device and test system of a semiconductor memory device
    3.
    发明申请
    Semiconductor memory device and test system of a semiconductor memory device 审中-公开
    一种半导体存储器件的半导体存储器件和测试系统

    公开(公告)号：US20090044063A1

    公开(公告)日：2009-02-12

    申请号：US11974342

    申请日：2007-10-12

    Applicant: Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

    Inventor： Yong-Hwan Cho ,  Byung-Heon Kwak ,  Hyun-Soon Jang ,  Jae-Hoon Joo ,  Seung-Whan Seo ,  Jong-Hyoung Lim

    IPC: G01R31/3177 ,  G06F11/25

    CPC classification number: G11C29/56 ,  G11C29/56008 ,  G11C2029/2602 ,  G11C2029/5602

    Abstract: A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.

    Abstract translation: 半导体存储器件包括存储器核心单元，N个数据输出缓冲器，N个数据输出端口以及多个测试逻辑电路。 存储核心单元通过N条数据线存储测试数据。 N个数据输出缓冲器分别连接到相应的N个数据线。 N个数据输出端口连接到相应的N个数据输出缓冲器，并分别与外部测试仪交换测试数据。 多个测试逻辑电路通过来自N条数据线的K条数据线接收测试数据，对所接收的测试数据进行测试逻辑运算，并提供一个数据输出缓冲器控制信号，该信号确定N个数据输出缓冲器的激活 测试模式下的数据输出缓冲区。 半导体存储器件降低了测试周期。

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