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    Electronic device for configuring neural network
    81.
    发明授权
    Electronic device for configuring neural network 有权

    公开(公告)号：US11335399B2

    公开(公告)日：2022-05-17

    申请号：US17011929

    申请日：2020-09-03

    Applicant: Postech Research and Business Development Foundation

    Inventor： Jinseok Kim ,  Yulhwa Kim ,  Jae-Joon Kim ,  Hyungjun Kim

    IPC: G11C11/41 ,  G06N3/08 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

    Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

    APPARATUS FOR LOW POWER TERNARY LOGIC CIRCUIT
    84.
    发明申请
    APPARATUS FOR LOW POWER TERNARY LOGIC CIRCUIT 有权

    公开(公告)号：US20220109444A1

    公开(公告)日：2022-04-07

    申请号：US17175570

    申请日：2021-02-12

    Applicant: POSTECH Research and Business Development Foundation

    Inventor： Seokhyeong KANG ,  Sunghye PARK ,  SungYun LEE ,  Sunmean KIM

    IPC: H03K19/00 ,  H01L51/05 ,  G06F30/327 ,  G06F30/337

    Abstract: A static ternary gate is disclosed. The static ternary gate includes a drain-ground path configured to output a drain voltage through a first transistor when a first pull-up circuit is turned on, and output a ground voltage through a second transistor when a first pull-down circuit is turned on, a half-drain path configured to output a half-drain voltage through the first transistor and the second transistor when both a second pull-up circuit and a second pull-down circuit are turned on. The first transistor is configured to connect a node between the first pull-up circuit and the second pull-down circuit to an output terminal, and the second transistor is configured to connect a node between the second pull-up circuit and the first pull-down circuit to the output terminal.

    METHOD FOR PREPARING PEROVSKITE NANOPARTICLE USING FLUIDIC CHANNEL
    87.
    发明申请
    METHOD FOR PREPARING PEROVSKITE NANOPARTICLE USING FLUIDIC CHANNEL 有权

    公开(公告)号：US20220017376A1

    公开(公告)日：2022-01-20

    申请号：US17373964

    申请日：2021-07-13

    Applicant: POSTECH Research and Business Development Foundation

    Inventor： Yongyoung NOH ,  Yongki KIM ,  Jisu HONG ,  Hyein KIM

    IPC: C01D17/00 ,  B01F5/04 ,  B01F3/08

    Abstract: Disclosed is a method for preparing a perovskite nanoparticle using a fluidic channel including a first step of forming a fluidic channel including a first outer tube, a second outer tube, and a storage tube capable of introducing flows of fluids, a second step of inducing formation of the perovskite nanoparticles by continuously preparing a mixed fluid with a laminar flow based on a flow rate by introducing a flow of a base fluid into the first outer tube, and introducing a flow of a dispersion fluid in the same direction as the flow of the base fluid into the second outer tube, and a third step of separating the perovskite nanoparticles from the mixed fluid stored in the storage tube.

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