公开(公告)号：US20200242456A1

公开(公告)日：2020-07-30

申请号：US16751503

申请日：2020-01-24

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seokhyeong KANG ,  Yesung KANG ,  Sunghoon KIM ,  Yoonho PARK

IPC: G06N3/063 ,  G06F9/50 ,  G06F9/30

Abstract: A neural network accelerator includes an operator that calculates a first operation result based on a first tiled input feature map and first tiled filter data, a quantizer that generates a quantization result by quantizing the first operation result based on a second bit width extended compared with a first bit width of the first tiled input feature map, a compressor that generates a partial sum by compressing the quantization result, and a decompressor that generates a second operation result by decompressing the partial sum, the operator calculates a third operation result based on a second tiled input feature map, second tiled filter data, and the second operation result, and an output feature map is generated based on the third operation result.

公开(公告)号：US20220352893A1

公开(公告)日：2022-11-03

申请号：US17489624

申请日：2021-09-29

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seokhyeong KANG ,  Sunmean KIM ,  SungYun LEE ,  Sunghye PARK

IPC: H03K19/0944 ,  H03K19/20

Abstract: A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.

公开(公告)号：US20200210637A1

公开(公告)日：2020-07-02

申请号：US16714583

申请日：2019-12-13

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seokhyeong KANG ,  Sunmean KIM ,  Sung-Yun LEE

IPC: G06F30/327 ,  H03K19/094 ,  H03K19/0944

Abstract: Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.

公开(公告)号：US20230170907A1

公开(公告)日：2023-06-01

申请号：US18060223

申请日：2022-11-30

Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Seokhyeong KANG ,  Youngchang CHOI ,  Sunmean KIM ,  Kyongsu LEE

IPC: H03K19/094 ,  H03K19/0185 ,  H03K19/0944 ,  G11C11/41

CPC classification number: H03K19/09425 ,  H03K19/0185 ,  H03K19/0944 ,  G11C11/41

Abstract: Disclosed is an inverter which includes a first P-MOS transistor connected between a node receiving a drain voltage and a first path node and operated based on an input voltage, a first N-MOS transistor connected between the first path node and an output terminal outputting an output voltage and operated based on the drain voltage, a second P-MOS transistor connected between the output terminal and a second path node and operated based on a ground voltage, a second N-MOS transistor connected between the second path node and a node receiving the ground voltage and operated based on the input voltage, a third P-MOS transistor connected between the first path node and the second path node and operated based on the input voltage, and a third N-MOS transistor connected between the first path node and the second path node and operated based on the input voltage.

公开(公告)号：US20220350568A1

公开(公告)日：2022-11-03

申请号：US17489629

申请日：2021-09-29

Applicant: Postech Research and Business Development Foundation

Inventor： Seokhyeong KANG ,  Sunmean KIM ,  Sunghye PARK ,  SungYun LEE

IPC: G06F7/502 ,  H03K19/173

Abstract: A circuit includes a first full adder, a second full adder, a first half adder, a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder, a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder, a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder, and a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder.

公开(公告)号：US20230127162A1

公开(公告)日：2023-04-27

申请号：US17969123

申请日：2022-10-19

Applicant: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY) ,  POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

Inventor： Kibog PARK ,  Seokhyeong KANG ,  Sungchul JUNG ,  Jinyoung PARK ,  Jaehyeong JO ,  Junhyung KIM ,  Wonho SONG

IPC: H01L27/11597

Abstract: Provided are a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a substrate, a plurality of word lines extending in a first direction on the substrate, a plurality of ferroelectric patterns respectively provided on the word lines, a blocking insulating film covering the ferroelectric patterns, a plurality of bit line pairs including a first bit line and a second bit line extending in a second direction crossing the word lines and the ferroelectric patterns on the blocking insulating film and intersecting the first direction, and a channel pattern provided between the first bit line and the second bit line of each of the bit line pairs on the blocking insulating film, wherein the channel pattern has an ambipolar conduction characteristic.

公开(公告)号：US20220109444A1

公开(公告)日：2022-04-07

申请号：US17175570

申请日：2021-02-12

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seokhyeong KANG ,  Sunghye PARK ,  SungYun LEE ,  Sunmean KIM

IPC: H03K19/00 ,  H01L51/05 ,  G06F30/327 ,  G06F30/337

Abstract: A static ternary gate is disclosed. The static ternary gate includes a drain-ground path configured to output a drain voltage through a first transistor when a first pull-up circuit is turned on, and output a ground voltage through a second transistor when a first pull-down circuit is turned on, a half-drain path configured to output a half-drain voltage through the first transistor and the second transistor when both a second pull-up circuit and a second pull-down circuit are turned on. The first transistor is configured to connect a node between the first pull-up circuit and the second pull-down circuit to an output terminal, and the second transistor is configured to connect a node between the second pull-up circuit and the first pull-down circuit to the output terminal.