公开(公告)号：US20200210637A1

公开(公告)日：2020-07-02

申请号：US16714583

申请日：2019-12-13

Applicant: POSTECH Research and Business Development Foundation

Inventor： Seokhyeong KANG ,  Sunmean KIM ,  Sung-Yun LEE

IPC: G06F30/327 ,  H03K19/094 ,  H03K19/0944

Abstract: Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.