公开(公告)号：US07982505B2

公开(公告)日：2011-07-19

申请号：US12518793

申请日：2007-12-12

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: H03K19/20 ,  G11C8/00

CPC classification number: H03K19/0016 ,  G11C7/22 ,  G11C7/225 ,  G11C8/10 ,  G11C8/18 ,  G11C2207/2227 ,  H03K19/20

Abstract: Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.

Abstract translation: 公开了一种逻辑电路，包括接收第一脉冲信号和第一选择信号的第一NAND门，反相第一NAND门的输出信号以输出结果信号的第一反相器门，接收第二NAND门的第二NAND门 脉冲信号和第一选择信号;第二反相器门，反相第二与非门的输出信号;第一PMOS晶体管，漏极端连接到第一与非门的输出;栅极， 第二NAND门和连接到电源电压的源极端子，以及第一NMOS晶体管，漏极端子连接到第一反相器栅极的输出，栅极端子连接到第二反相器栅极的输出端，源极端子连接 到地下潜力。

公开(公告)号：US20110142231A1

公开(公告)日：2011-06-16

申请号：US12926775

申请日：2010-12-08

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: H04L9/30

CPC classification number: G06F7/72 ,  G06F2207/7204 ,  H04L9/3033 ,  H04L2209/56

Abstract: A prime number generating device is provided that includes a computation unit capable of performing at least addition and division on data of a predetermined number of bits or less; a prime number candidate data generating unit that generates prime number candidate data with a larger number of bits than the predetermined number of bits; a partitioned prime number candidate data generating unit that generates a plurality of partitioned prime number candidate data elements by partitioning the prime number candidate data; and a determination data generating unit that generates determination data for determining whether or not the prime number candidate expressed by the prime number candidate data is a composite number by using the computation unit to add together the respective plurality of partitioned prime number candidate data elements.

Abstract translation: 提供一种质数产生装置，其包括能够至少对预定位数或更少的数据进行加法和除法的计算单元; 素数候选数据生成单元，生成比预定位数大的位数的素数候选数据; 分割素数候选数据生成单元，其通过分割素数候选数据来生成多个分割的素数候选数据元素; 以及确定数据生成单元，其生成用于通过使用所述计算单元来确定由所述素数候选数据表示的素数候选数据是否为合成数量的确定数据，以将相应的多个分割的素数候选数据元素相加在一起。

公开(公告)号：US20110032741A1

公开(公告)日：2011-02-10

申请号：US12910536

申请日：2010-10-22

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C7/10 ,  G11C7/08 ,  G11C5/06

CPC classification number: G11C11/412

Abstract: The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2 using the storage node V1 as an input and the storage node V2 as an output, an access transistor N3 connected between a read bit line RBL and the storage node V1, and an access transistor N4 connected between a write bit line WBL and the storage node V2. When the access transistor N4 is controlled by a write word line WWL, the access transistor N4 can be used as holding control means and writing means for the memory cell, making it possible to obtain a semiconductor device capable of operating at a high speed with a small number of elements.

Abstract translation: SRAM单元由使用存储节点V2作为输入的反相器电路（P1，N1）和作为输出的存储节点V1，使用存储节点连接在电源VDD与存储节点V2之间的负载晶体管P2 V1作为输入，存储节点V2作为输出，连接在读取位线RBL和存储节点V1之间的存取晶体管N3以及连接在写位线WBL与存储节点V2之间的存取晶体管N4。 当访问晶体管N4由写入字线WWL控制时，存取晶体管N4可以用作存储单元的保持控制装置和写入装置，使得可以获得能够以高速操作的半导体器件 少数元素。

公开(公告)号：US20100149887A1

公开(公告)日：2010-06-17

申请号：US12067265

申请日：2006-09-27

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C5/147 ,  G11C11/417

Abstract: A voltage generator that monitors a writing margin as a control amount in order to carry out an optimum power source control when control of a SRAM cell power source is carried out at writing operation, and always keeps the writing margin constant; and a power source selector are included to switch power source voltage at writing. By switching the power source voltage at writing, a semiconductor memory device in which a stable writing operation is achieved without largely deteriorating writing time in the SRAM cell and an ultrahigh speed operation or ultralow power operation can be carried out is obtained.

Abstract translation: 将写入裕量作为控制量进行监视的电压发生器，以便在写入动作时进行SRAM单元电源的控制时，进行最佳的电源控制，并始终保持写入余量不变; 并且包括电源选择器以在写入时切换电源电压。 通过在写入时切换电源电压，可以实现其中实现稳定写入操作而不会使SRAM单元中的写入时间大大恶化以及超高速操作或超低功耗操作的半导体存储器件。

公开(公告)号：US20090172415A1

公开(公告)日：2009-07-02

申请号：US12331587

申请日：2008-12-10

Applicant: Koichi TAKEDA

Inventor： Koichi TAKEDA

IPC: G06F12/14

CPC classification number: G06F12/1408

Abstract: The control unit includes a CPU which generates an access signal for performing writing or reading on the external memory, encryption/decryption means which, when the access signal is used for writing, encrypts an address designated by the CPU to generate a write address and encrypts write data contained in the access signal to generate write encrypted data, and which, when the access signal is used for reading, encrypts an address designated by the CPU to generate a read address and decrypts the encrypted data read from the external memory to generate plaintext data, and external control means which writes the write encrypted data in a position designated by the write address generated by the encryption/decryption means and which reads the encrypted data from a position designated by the read address generated by the encryption/decryption means and supplies the same to the encryption/decryption means for its decryption.

Abstract translation: 控制单元包括生成用于在外部存储器上进行写入或读取的访问信号的CPU，加密/解密装置，当访问信号用于写入时，加密由CPU指定的地址以产生写入地址并加密 写入访问信号中包含的数据以产生写入加密数据，当访问信号用于读取时，加密由CPU指定的地址以生成读取地址并对从外部存储器读取的加密数据进行解密以产生明文 数据和外部控制装置，其将写入加密数据写入由加密/解密装置生成的写入地址指定的位置，并且从由加密/解密装置产生的读取地址指定的位置读取加密数据， 与加密/解密手段相同，用于其解密。

公开(公告)号：US07532536B2

公开(公告)日：2009-05-12

申请号：US10577398

申请日：2004-09-17

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C8/00 ,  G11C7/10 ,  G11C11/00

CPC classification number: G11C11/412 ,  H01L27/11

Abstract: The SRAM cells of a semiconductor storage device each comprise first and second inverter circuits loop-connected with each other to form a hold circuit; two access transistors; and a hold control transistor connected in series with a drive transistor of the second inverter circuit. While the memory cell is not accessed, the hold control transistor causes the first and second inverter circuits to form the loop connected hold circuit for statically holding data. When the memory cell is accessed, the hold control transistor causes the first and second inverter circuits to be disconnected from the loop connection for dynamically holding data, thereby preventing data corruption that would otherwise possible occur due to a read operation. Moreover, a sense amplifier circuit that uses a single bit line to read data from a memory cell is disposed in a space appearing in the memory cell array, thereby effectively using the area.

Abstract translation: 半导体存储装置的SRAM单元各自包括彼此环路连接的第一和第二反相器电路，以形成保持电路; 两个存取晶体管; 以及与第二反相器电路的驱动晶体管串联连接的保持控制晶体管。 当存储单元不被访问时，保持控制晶体管使得第一和第二反相器电路形成用于静态保持数据的环路保持电路。 当存储单元被访问时，保持控制晶体管使得第一和第二反相器电路与循环连接断开，用于动态保持数据，从而防止由于读取操作而可能发生的数据损坏。 此外，使用单个位线从存储单元读取数据的读出放大器电路设置在出现在存储单元阵列中的空间中，从而有效地使用该区域。

公开(公告)号：US07446562B2

公开(公告)日：2008-11-04

申请号：US11628532

申请日：2005-05-25

Applicant: Masahiro Nomura ,  Koichi Takeda

Inventor： Masahiro Nomura ,  Koichi Takeda

IPC: H01L25/00 ,  H03K19/177

CPC classification number: H03K19/17748 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17792

Abstract: A programmable semiconductor device of the invention includes: processing element unit executing a predetermined operation; input/output connection unit acting as a signal input part and/or a signal output part in processing element unit; interconnecting unit, comprised of a plurality of wires, connecting processing element unit via input/output connection unit; bidirectional repeater unit, arranged between the intersection points of interconnecting unit, performing disconnection, or driving interconnecting unit in the forward direction or in the reverse direction; and interconnection connecting unit, arranged at the intersection point, connecting interconnecting unit at the intersection point.

Abstract translation: 本发明的可编程半导体器件包括：执行预定操作的处理元件单元; 用作信号输入部分的输入/输出连接单元和/或处理元件单元中的信号输出部分; 由多根电线组成的互连单元，经由输入/输出连接单元连接处理元件单元; 双向中继器单元，布置在互连单元的交点之间，在正向或反向上执行断开或驱动互连单元; 和互连连接单元，布置在交点处，交叉点处连接互连单元。

公开(公告)号：US07302646B2

公开(公告)日：2007-11-27

申请号：US10072532

申请日：2002-02-06

Applicant: Hiroshi Nomiyama ,  Koichi Takeda ,  Takashi Sakairi

Inventor： Hiroshi Nomiyama ,  Koichi Takeda ,  Takashi Sakairi

IPC: G06F3/00

CPC classification number: G06F17/30991 ,  G06F17/3089 ,  Y10S707/99943 ,  Y10S715/968

Abstract: An information processing system, for processing information obtained from multiple sites that are connected via the Internet 10, includes: a webcrawler 13, for crawling sites, across the Internet 10, which are registered in a registered site DB 11; a metadata DB 12, for storing metadata from which information elements are extracted from content referred to by using a URL; an important information element extraction mechanism 30, for reading information stored in the metadata DB 12, and for extracting important information elements based on the matching level of information elements; an important information element DB 40, for storing the extracted important information elements; and a result display mechanism 41, for visually presenting said stored important information elements.

Abstract translation: 一种用于处理通过因特网10连接的多个站点获得的信息的信息处理系统，包括：用于爬行站点的网络抓取器13，其跨越因特网10登记在注册站点DB 11中; 元数据DB 12，用于存储从使用URL引用的内容中提取信息元素的元数据; 一种重要的信息元素提取机构30，用于读取存储在元数据DB 12中的信息，并且用于基于信息元素的匹配级别提取重要的信息元素; 用于存储提取的重要信息元素的重要信息元素DB 40; 以及结果显示机构41，用于可视地呈现所存储的重要信息元素。

公开(公告)号：US20070132009A1

公开(公告)日：2007-06-14

申请号：US10575631

申请日：2004-09-29

Applicant: Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

Inventor： Kiyoshi Takeuchi ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe

IPC: H01L29/788

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

Abstract translation: 一种半导体器件，包括：MIS型场效应晶体管，其包括从衬底平面突出的半导体凸起部分，从半导体凸起部分顶部延伸到半导体凸起部分的相对侧面上的栅电极，栅极绝缘膜 存在于栅极电极和半导体凸起部分之间，以及设置在半导体凸起部分中的源极和漏极区域; 设置在包括晶体管的基板上的层间绝缘膜; 以及通过用导体填充形成在所述层间绝缘膜中的沟槽而形成的掩埋导体互连，其中所述掩埋导体布线连接所述半导体凸起部分的所述源极和漏极区域中的一个以及所述层间绝缘膜下方的另一个导电部分 。

公开(公告)号：US20070073698A1

公开(公告)日：2007-03-29

申请号：US11528932

申请日：2006-09-27

Applicant: Hiroshi Kanayama ,  Hiroshi Nomiyama ,  Koichi Takeda

Inventor： Hiroshi Kanayama ,  Hiroshi Nomiyama ,  Koichi Takeda

IPC: G06F17/30

CPC classification number: G06F21/62 ,  G06F2221/2141

Abstract: An apparatus which manages confidentiality of information. This apparatus includes: a recording unit operable to record information in association with a history of users having accessed the information, or, with access rights defining users able to access the information; a generating unit operable to generate management information indicating whether the information should be managed confidentially from users not permitted to access the information; a selecting unit operable to select, based on the history or access rights, users able to access the information; and a notifying unit operable to notify the selected users of the generated management information in association with identification information of the information.

Abstract translation: 管理信息机密性的设备。 该装置包括：记录单元，其可操作以与访问该信息的用户的历史相关联地记录信息，或者具有定义能够访问该信息的用户的访问权限; 生成单元，其可操作用于生成管理信息，该管理信息指示是否应该从不允许访问所述信息的用户保密地管理所述信息; 选择单元，其可操作以基于所述历史或访问权限来选择能够访问所述信息的用户; 以及通知单元，其可操作以将所生成的管理信息与所述信息的识别信息相关联地通知所选择的用户。