公开(公告)号：US5544070A

公开(公告)日：1996-08-06

申请号：US937331

申请日：1992-08-27

Applicant: William D. Cox ,  Andrew K. L. Chan ,  Richard J. Wong ,  James M. Apland ,  Kathryn E. Gordon

Inventor： William D. Cox ,  Andrew K. L. Chan ,  Richard J. Wong ,  James M. Apland ,  Kathryn E. Gordon

IPC: G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H03K19/177

CPC classification number: H03K19/17764 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H03K19/17704 ,  H03K19/1778 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A programmable device comprises a first antifuse programmed with a first programming method and a second antifuse programmed with a second programming method, whereby an actual operating current flowing through the second antifuse exceeds a maximum permissible operating current of the first antifuse but does not exceed a maximum permissible operating current of the second antifuse, whereby an actual operating current flowing through the first antifuse does not exceed the maximum permissible operating current of the first antifuse, and whereby an actual operating current flowing through the second antifuse does not exceed the maximum permissible operating current of the second antifuse. By allowing the use of a programming method on some antifuses which would not be adequate for the programming of other antifuses, the realization of user-specific circuits in field programmable devices is facilitated and the reliability of user-specific circuits realized in field programmable devices is enhanced.

Abstract translation: 可编程器件包括用第一编程方法编程的第一反熔丝和用第二编程方法编程的第二反熔丝，由此流过第二反熔丝的实际工作电流超过第一反熔丝的最大允许工作电流但不超过最大值 第二反熔丝的允许工作电流，由此流过第一反熔丝的实际工作电流不超过第一反熔丝的最大允许工作电流，由此流过第二反熔丝的实际工作电流不超过最大允许工作电流 的第二个反熔丝。 通过允许在一些反熔丝上使用编程方法来编程其他抗反熔丝，对于现场可编程器件中的用户特定电路的实现是有利的，并且在现场可编程器件中实现的用户特定电路的可靠性是 增强。

公开(公告)号：US5424655A

公开(公告)日：1995-06-13

申请号：US246527

申请日：1994-05-20

Applicant: Hua-Thye Chua

Inventor： Hua-Thye Chua

IPC: G11C17/18 ,  H03K19/177

CPC classification number: H03K19/17776 ,  G11C17/18 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17792

Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

Abstract translation: 随着处理技术的进步，可编程ASIC架构允许与设备的其他部分一起减少编程晶体管的尺寸。 编程使能电路用于允许在反熔丝的编程中使用具有较少位的编程地址移位寄存器。 公开了同时编程多个对应的反熔丝以加速ASIC编程的方法。 架构方面允许消除模块中的数字逻辑元件的输出保护，要消除一些测试晶体管，要降低其他测试晶体管的尺寸，减少互连线段上的电容，要消除的一些编程晶体管， 并减小其他编程晶体管的尺寸。

公开(公告)号：US5293133A

公开(公告)日：1994-03-08

申请号：US937071

申请日：1992-08-27

Applicant: John M. Birkner ,  David T. Martin ,  Richard J. Wong

Inventor： John M. Birkner ,  David T. Martin ,  Richard J. Wong

IPC: G11C17/16 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C29/027 ,  G11C17/16 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50008 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A method for determining an electrical characteristic (such as a resistance) of an antifuse of a programmable device. The method comprises the steps of: 1) before the antifuse is programmed, determining an electrical characteristic (such as a voltage, current and/or resistance) of a first conductive path which includes a series element disposed electrically in series with a parallel element, the parallel element being controlled to be substantially conductive, the parallel element being disposed electrically in parallel with the unprogrammed antifuse; 2) after programming of the antifuse, determining an electrical characteristic (such as a voltage, current and/or resistance) of a second conductive path including the series element disposed electrically in series with the programmed antifuse when the parallel element is controlled to be substantially nonconductive; 3) determining an electrical characteristic (such as a voltage, current and/or resistance) of a third, conductive path through the series element, and through the programmed antifuse and the parallel element, the parallel element being controlled to be substantially conductive; and 4) determining the electrical characteristic (such as a resistance) of the antifuse based on the above three determinations in 1), 2) and 3). The method is usable to determine whether or not programmed antifuses of a programmable device have low enough resistances to meet desired reliability criteria.

Abstract translation: 一种用于确定可编程器件的反熔丝的电特性（例如电阻）的方法。 该方法包括以下步骤：1）在对反熔丝进行编程之前，确定第一导电路径的电特性（例如电压，电流和/或电阻），其包括与并联元件串联设置的串联元件， 所述并联元件被控制为基本导电，所述并联元件与所述未编程的反熔丝电平行地布置; 2）在对反熔丝进行编程之后，确定包括串联元件的第二导电路径的电特性（例如电压，电流和/或电阻），该第二导电路径包括与编程的反熔丝串联设置的串联元件， 非导电; 3）确定通过串联元件的第三导电路径的电特性（例如电压，电流和/或电阻），以及通过编程的反熔丝和并联元件，所述并联元件被控制为基本导电; 以及4）基于上述3）中确定的反熔丝的电特性（如电阻）。 该方法可用于确定可编程器件的编程反熔丝是否具有足够低的电阻以满足期望的可靠性标准。

公开(公告)号：US5280202A

公开(公告)日：1994-01-18

申请号：US24986

申请日：1993-03-02

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

公开(公告)号：US20240171178A1

公开(公告)日：2024-05-23

申请号：US18504072

申请日：2023-11-07

Applicant: QuickLogic Corporation

Inventor： Ket Chong Yap ,  Chihhung Liao

IPC: H03K19/1776 ,  G11C11/419 ,  H03K19/20

CPC classification number: H03K19/1776 ,  G11C11/419 ,  H03K19/20

Abstract: An area efficient readable and resettable configuration memory latch is disclosed that maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL drives data to be written, while, during read operations, enabled by a Word Line Read (WLR) signal, the state of the BL is indicative of a data stored in the latch. A pull-down network is activated when the WLR signal is asserted and the stored data is logic one and, when activated, operates to pull down the BL to logic zero; the pull-down network is inactive otherwise. A weak pull-up operates to pull up the BL when the pull-down network is inactive. A sensing block is configured to sense the state of the BL when the WLR signal and a read enable signal are both asserted.

公开(公告)号：US20240170087A1

公开(公告)日：2024-05-23

申请号：US18504078

申请日：2023-11-07

Applicant: QuickLogic Corporation

Inventor： Ket Chong Yap ,  Chihhung Liao ,  Shieh Huan Yen

IPC: G11C29/32 ,  G11C29/12 ,  G11C29/20 ,  H03K19/173 ,  H03K19/17728

CPC classification number: G11C29/32 ,  G11C29/1201 ,  G11C29/20 ,  H03K19/1737 ,  H03K19/17728 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/3202

Abstract: A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.

公开(公告)号：US11935618B2

公开(公告)日：2024-03-19

申请号：US17725564

申请日：2022-04-21

Applicant: QuickLogic Corporation

Inventor： Ket Chong Yap ,  Chihhung Liao ,  Shieh Huan Yen

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  H03K19/017

CPC classification number: G11C7/1039 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  H03K19/01742

Abstract: An area efficient input terminated readable and resettable configuration memory latch is disclosed. A pull-up network and a pair of pull-down networks operate to set the value of an internal node based, in part, on the state of the input terminated bit line and a word line write input. The internal node is inverted to form the output of the configuration memory latch. A reset line operates to reset the latch and a reset cycle is initiated prior to each write cycle. In some embodiments, the configuration memory latch includes a scan mode input, which, when asserted, facilitates automated testing of a programmable logic device that includes the configuration memory latch. Asserting the scan mode input enables Design for Test functionality. A sensing block is configured to sense the state of the bit when a word line read signal and a read enable signal are both asserted.

公开(公告)号：US11652486B1

公开(公告)日：2023-05-16

申请号：US17697862

申请日：2022-03-17

Applicant: QuickLogic Corporation

Inventor： Ket Chong Yap ,  Chihhung Liao

IPC: H03K19/1776 ,  H03K19/17704 ,  H03K19/17736

CPC classification number: H03K19/1776 ,  H03K19/1774 ,  H03K19/17708 ,  H03K19/17744

Abstract: A bit line (BL) may be coupled at a first end to a BL driver (BLD) and at a second end to a BL receiver (BLR). The BL include a plurality of sections and each BL section may be coupled to at least one corresponding sectional configuration memory latch controlled by: at least one sectional word line write (WLW-k) signal, which when asserted enables data to be written into the at least one corresponding sectional configuration memory latch when a corresponding tri-stateable sectional driver (SD-k) is activated, and at least one sectional word line read (WLR-k) signal, which when asserted enables data to be from the at least one corresponding sectional configuration memory latch when the corresponding sectional pull-up (PU-k) is activated.

公开(公告)号：US10456053B2

公开(公告)日：2019-10-29

申请号：US15054022

申请日：2016-02-25

Applicant: QuickLogic Corporation

Inventor： Amir Abbas Emadzadeh

IPC: A61B5/024 ,  A61B5/00

Abstract: A wrist worn heart rate monitor includes a photoplethysmogram (PPG) sensor and an inertial sensor. Signals from the inertial sensor are used to identify and remove noise from the PPG signals. An initial heart rate value is selected from a number of heart rate candidates that remain in the resulting PPG spectrum and is used to track the heart rate of the user. The PPG spectrum is monitored while tracking the heart rate to determine if the selected initial heart rate value is in error. The PPG spectrum may be monitored by determining a correlation of possible heart rate candidates in each PPG spectrum to the previous heart rate candidates and resetting the heart rate value accordingly. Additionally or alternatively, the PPG spectrum may be monitored by determining when only a single heart rate candidate is present in consecutive PPG spectra and resetting the heart rate value accordingly.

公开(公告)号：US20080094103A1

公开(公告)日：2008-04-24

申请号：US11551201

申请日：2006-10-19

Applicant: Ajithkumar V. Dasari ,  Wilma Waiman Shiao ,  Tarachand G. Pagarani

Inventor： Ajithkumar V. Dasari ,  Wilma Waiman Shiao ,  Tarachand G. Pagarani

IPC: H03K19/177

CPC classification number: H03K19/1737

Abstract: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A1, A2, . . . , Aj, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.

Abstract translation: 提供了使用具有一半输入端口的多路复用器的多路复用器功能的实现，因为它具有可能的输出值。 具有两个数据输入端口的多路复用器执行多路复用器的功能，该多路复用器具有四个预定的数据输入信号（A 1，N 2，A 3，A 3， A 4 ）。 通常，仅具有m个数据输入端口的多路复用器执行具有两倍于预定数据输入信号A 1，A 2 2的复用器的功能。 。 。 ，其中j = m * 2。 多路复用器功能可以使用具有一个或多个宏小区的可编程设备，逆变器以及诸如反熔丝的开关来实现。