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    Logic module for field programmable gate array
    1.
    发明授权
    Logic module for field programmable gate array 失效
    现场可编程门阵列逻辑模块

    公开(公告)号：US5682106A

    公开(公告)日：1997-10-28

    申请号：US755758

    申请日：1996-09-18

    Applicant: William D. Cox ,  Benjamin W. Blair ,  Paige A. Kolze ,  Hua-Thye Chua

    Inventor： William D. Cox ,  Benjamin W. Blair ,  Paige A. Kolze ,  Hua-Thye Chua

    IPC: G11C17/18 ,  H03K19/177 ,  H03K7/38 ,  H03K19/173

    CPC classification number: H03K19/17776 ,  G11C17/18 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17792

    Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

    Abstract translation: 随着处理技术的进步，可编程ASIC架构允许与设备的其他部分一起减少编程晶体管的尺寸。 编程使能电路用于允许在反熔丝的编程中使用具有较少位的编程地址移位寄存器。 公开了同时编程多个对应的反熔丝以加速ASIC编程的方法。 架构方面允许消除模块中的数字逻辑元件的输出保护，要消除一些测试晶体管，要降低其他测试晶体管的尺寸，减少互连线段上的电容，要消除的一些编程晶体管， 并减小其他编程晶体管的尺寸。

    Electrically programmable interconnect structure having a PECVD amorphous silicon element
    2.
    发明授权
    Electrically programmable interconnect structure having a PECVD amorphous silicon element 失效
    具有PECVD非晶硅元件的电可编程互连结构

    公开(公告)号：US5502315A

    公开(公告)日：1996-03-26

    申请号：US161504

    申请日：1993-12-02

    Applicant: Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

    Inventor： Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

    IPC: H01L23/525 ,  H02L27/02

    CPC classification number: H01L23/5252 ,  H01L2924/0002

    Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

    Abstract translation: 在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。 非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。 在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。 在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。 在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。 选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。 还描述了用于形成具有反熔丝的现场可编程门阵列的方法。

    Programmable write-once, read-only semiconductor memory array using SCR current sink and current source devices
    4.
    发明授权
    Programmable write-once, read-only semiconductor memory array using SCR current sink and current source devices 失效
    可编程只读半导体存储器阵列，使用SCR电流源和电流源器件

    公开(公告)号：US4130889A

    公开(公告)日：1978-12-19

    申请号：US792940

    申请日：1977-05-02

    Applicant: Hua-Thye Chua

    Inventor： Hua-Thye Chua

    IPC: G11C17/16 ,  G11C17/18 ,  H01L27/102 ,  G11C17/06 ,  G11C7/00

    CPC classification number: G11C17/18 ,  G11C17/16 ,  H01L27/1027

    Abstract: This disclosure relates to a programmable write-once, read-only semiconductor memory array which has an improved current source for each bit line and an improved current sink for each Word line. This programmable write-once, read-only semiconductor memory array utilizes a SCR (PNPN or NPNP) or the end of each Word line of the array to function as a current sink to minimize voltage drop on the Word line and a SCR (PNPN or NPNP) on each Bit line of the array for current sourcing purposes. This disclosure also relates to an integrated SCR (PNPN or NPNP) for use with a plurality of connected semiconductor devices to provide either a current sourcing or current sinking or drawing function for the plurality of connected semiconductor devices.

    Abstract translation: 本公开涉及一种可编程一次写入的只读半导体存储器阵列，其具有用于每个位线的改进的电流源和用于每个字线的改进的电流吸收器。 该可编程一次写入只读半导体存储器阵列利用SCR（PNPN或NPNP）或阵列的每个字线的末端用作电流吸收器，以最小化字线和SCR（PNPN或 NPNP）在阵列的每个位线上用于当前采购目的。 本公开还涉及用于与多个连接的半导体器件一起使用的集成SCR（PNPN或NPNP），以为多个连接的半导体器件提供电流源或电流吸收或绘图功能。

    Programmable application specific integrated circuit employing antifuses and methods therefor
    7.
    发明授权
    Programmable application specific integrated circuit employing antifuses and methods therefor 失效

    公开(公告)号：US5892684A

    公开(公告)日：1999-04-06

    申请号：US892304

    申请日：1997-07-14

    Applicant: Hua-Thye Chua

    Inventor： Hua-Thye Chua

    IPC: G11C17/18 ,  H03K19/177 ,  G06F17/50

    CPC classification number: H03K19/17776 ,  G11C17/18 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17792

    Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

    Programmable application specific integrated circuit employing antifuses and methods therefor
    9.
    发明授权
    Programmable application specific integrated circuit employing antifuses and methods therefor 失效
    采用反熔丝的可编程专用集成电路及其方法

    公开(公告)号：US5654649A

    公开(公告)日：1997-08-05

    申请号：US501644

    申请日：1995-07-12

    Applicant: Hua-Thye Chua

    Inventor： Hua-Thye Chua

    IPC: G11C17/18 ,  H03K19/177 ,  H03K19/00 ,  H03K19/173

    CPC classification number: H03K19/17776 ,  G11C17/18 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17792

    Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

    Abstract translation: 随着处理技术的进步，可编程ASIC架构允许与设备的其他部分一起减少编程晶体管的尺寸。 编程使能电路用于允许在反熔丝的编程中使用具有较少位的编程地址移位寄存器。 公开了同时编程多个对应的反熔丝以加速ASIC编程的方法。 架构方面允许消除模块中的数字逻辑元件的输出保护，要消除一些测试晶体管，要降低其他测试晶体管的尺寸，减少互连线段上的电容，要消除的一些编程晶体管， 并减小其他编程晶体管的尺寸。

    Programmable application specific integrated circuit and logic cell therefor
    10.
    发明授权
    Programmable application specific integrated circuit and logic cell therefor 失效
    可编程专用集成电路和逻辑单元

    公开(公告)号：US5220213A

    公开(公告)日：1993-06-15

    申请号：US847137

    申请日：1992-03-06

    Applicant: Andrew K. Chan ,  Hua-Thye Chua

    Inventor： Andrew K. Chan ,  Hua-Thye Chua

    IPC: H03K19/173 ,  H03K19/177

    CPC classification number: H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

    Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种功能强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

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