公开(公告)号：US07482834B2

公开(公告)日：2009-01-27

申请号：US11551201

申请日：2006-10-19

Applicant: Ajithkumar V. Dasari ,  Wilma Waiman Shiao ,  Tarachand G. Pagarani

Inventor： Ajithkumar V. Dasari ,  Wilma Waiman Shiao ,  Tarachand G. Pagarani

IPC: G06F7/38 ,  H03K19/177

CPC classification number: H03K19/1737

Abstract: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A1, A2, . . . , Aj, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.

Abstract translation: 提供了使用具有一半输入端口的多路复用器的多路复用器功能的实现，因为它具有可能的输出值。 具有两个数据输入端口的复用器执行具有四个预定数据输入信号（A1，A2，A3，A4）的多路复用器的功能。 通常，仅具有m个数据输入端口的复用器执行具有两倍于预定数据输入信号A1，A2的复用器的功能。 。 。 ，Aj，其中j = m * 2。 多路复用器功能可以使用具有一个或多个宏小区的可编程设备，逆变器以及诸如反熔丝的开关来实现。

公开(公告)号：US20080094103A1

公开(公告)日：2008-04-24

申请号：US11551201

申请日：2006-10-19

Applicant: Ajithkumar V. Dasari ,  Wilma Waiman Shiao ,  Tarachand G. Pagarani

Inventor： Ajithkumar V. Dasari ,  Wilma Waiman Shiao ,  Tarachand G. Pagarani

IPC: H03K19/177

CPC classification number: H03K19/1737

Abstract: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A1, A2, . . . , Aj, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.

Abstract translation: 提供了使用具有一半输入端口的多路复用器的多路复用器功能的实现，因为它具有可能的输出值。 具有两个数据输入端口的多路复用器执行多路复用器的功能，该多路复用器具有四个预定的数据输入信号（A 1，N 2，A 3，A 3， A 4 ）。 通常，仅具有m个数据输入端口的多路复用器执行具有两倍于预定数据输入信号A 1，A 2 2的复用器的功能。 。 。 ，其中j = m * 2。 多路复用器功能可以使用具有一个或多个宏小区的可编程设备，逆变器以及诸如反熔丝的开关来实现。

公开(公告)号：US06678646B1

公开(公告)日：2004-01-13

申请号：US09460069

申请日：1999-12-14

Applicant: David A. McConnell ,  Ajithkumar V. Dasari ,  Martin T. Mason

Inventor： David A. McConnell ,  Ajithkumar V. Dasari ,  Martin T. Mason

IPC: G06F1750

CPC classification number: G06F17/5068 ,  G06F17/5054

Abstract: A method for implementing the physical design for a dynamically reconfigurable logic circuit. The method is carried out using software that forms a physical design flow to take a design specification from a schematic or high-level description language (HDL) through to FPGA configuration bitstream files. The method involves reading a design netlist that was entered, the design netlist including a set of static macros and a set of reconfigurable macro contexts. Then, each of the reconfigurable macros are compiled and an initial device context is placed and routed. The device context is updated by arbitrarily selecting a context for each reconfigurable macro, placing and routing the updated device context and repeating the steps of updating, placing and routing until all of the reconfigurable macro contexts have been placed and routed. Then, after the compilation process is complete, full, partial, and incremental bitstream files are generated.

Abstract translation: 一种用于实现动态可重构逻辑电路的物理设计的方法。 该方法使用形成物理设计流程的软件进行，以从原理图或高级描述语言（HDL）到FPGA配置比特流文件进行设计规范。该方法涉及读取输入的设计网表，设计 网表包括一组静态宏和一组可重构的宏上下文。 然后，每个可重新配置的宏被编译并且初始设备上下文被放置和路由。 通过任意选择每个可重新配置的宏的上下文，放置和路由更新的设备上下文并重复更新，放置和布线的步骤直到所有可重新配置的宏上下文已被放置和路由来更新设备上下文。 然后，在编译过程完成后，将生成完整，部分和增量的位流文件。