公开(公告)号：US20020137272A1

公开(公告)日：2002-09-26

申请号：US10121694

申请日：2002-04-15

发明人： Mark A. Helm

IPC分类号： H01L021/8238 ,  H01L021/425 ,  H01L021/8234

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L21/823892

摘要： An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.

公开(公告)号：US20020094667A1

公开(公告)日：2002-07-18

申请号：US09760885

申请日：2001-01-17

申请人： ABB Research Ltd.

发明人： Mietek Bakowski ,  Ulf Gustafsson ,  Heinz Lendenmann

IPC分类号： H01L021/425

CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/7722 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of planar structure has a pn-junction (10) formed by a first layer (1) doped according to a first conductivity type, n or p, and on top thereof a second layer (2) doped according to a second conductivity type. The second layer has a higher doping concentration than the first layer and a lateral edge thereof is provided with an edge termination with second zones of said second conductivity type separated by first zones (4) of said first conductivity type arranged so that the total charge and/or the effective sheet charge density of dopants according to said second conductivity type is decreasing towards the laterally outer border (8) of the edge termination. A third layer (5) doped according to said first conductivity type is arranged on top of said second layer at least in the region of the edge termination for burying the edge termination of the device thereunder.

摘要翻译： 平面结构的半导体器件具有由根据第一导电类型n或p掺杂的第一层（1）形成的pn结（10），并且在其顶部上具有根据第二导电性掺杂的第二层（2） 类型。 第二层具有比第一层更高的掺杂浓度，并且其侧边缘设置有边缘终端，其中所述第二导电类型的第二区被所述第一导电类型的第一区（4）隔开，以使总电荷和 /或根据所述第二导电类型的掺杂剂的有效片电荷密度朝着边缘终端的横向外边界（8）减小。 根据所述第一导电类型掺杂的第三层（5）至少在边缘终端的区域中布置在所述第二层的顶部上，用于掩埋其下方的器件的边缘终端。

公开(公告)号：US20020090830A1

公开(公告)日：2002-07-11

申请号：US10092991

申请日：2002-03-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Seiji Inumiya ,  Yoshio Ozawa

IPC分类号： H01L021/336 ,  H01L021/76 ,  H01L021/425

CPC分类号： H01L21/28202 ,  H01L21/28185 ,  H01L21/2822 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/42368 ,  H01L29/518

摘要： A semiconductor device is provided in which a lowering in the breakdown voltage of a gate insulating film (nitrided silicon oxide film) in a boundary region between the upper-end corner portion of the side wall of an element isolating groove and a silicon substrate in the end portion of an element forming region which is formed in contact therewith can be suppressed without causing an increase in the number of steps (time for effecting the steps). An element isolation insulating film is filled into the internal portion of the element isolating groove to cover the end portion of the silicon substrate in the element forming region which is formed in contact with the upper-end portion of the side wall of the element isolating groove, nitrogen is selectively doped into the surface of the silicon substrate in a region of the element forming region other than the end portion thereof with the element isolation insulating film used as a mask, then a portion of the element isolation insulating film lying outside the element isolating groove is removed to expose the upper-end portion of the side wall, and a nitrided silicon oxide film used as the gate insulating film is formed by the heat treatment in an atmosphere containing an oxidizing agent.

公开(公告)号：US20020081764A1

公开(公告)日：2002-06-27

申请号：US09741350

申请日：2000-12-21

发明人： Anthony J. Springthorpe ,  Richard W. Streater ,  Aniket Joshi

IPC分类号： H01L021/00 ,  H01L021/425 ,  H01L021/20 ,  H01L021/36 ,  H01L031/0328 ,  H01L031/0336

CPC分类号： H01L33/305 ,  B82Y20/00 ,  H01L21/2205 ,  H01S5/305 ,  H01S5/34

摘要： A structure for doping of III-V compounds is provided. The structure is a multi-layered structure in which layers of dopant are alternated with layers of initially undoped III-V compound. Dopant diffuses from the layers of dopant into the layers of III-V compound. The structure does not facilitate the introduction of impurities into the III-V compound during the diffusion of the dopant.

摘要翻译： 提供掺杂III-V化合物的结构。 该结构是多层结构，其中掺杂剂层与最初未掺杂的III-V化合物的层交替。 掺杂剂从掺杂剂层扩散到III-V族化合物的层中。 该结构不容易在掺杂剂扩散期间将杂质引入到III-V族化合物中。

公开(公告)号：US20020072207A1

公开(公告)日：2002-06-13

申请号：US10013210

申请日：2001-12-07

发明人： Hideyuki Andoh

IPC分类号： H01L023/62 ,  H01L021/20 ,  H01L021/36 ,  H01L021/425

CPC分类号： H01L29/66136 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided, which prevents the development of localized breakdowns at the semiconductor sidewall, having a stabilized, desired breakdown voltage. It embraces a p-type third semiconductor region formed on a first main surface of an n-type semiconductor body; an n-type second semiconductor region selectively formed at the center of a second main surface; an n-type first semiconductor region formed between the third and the second semiconductor regions; and, n-type fourth semiconductor region surrounding the first and the second semiconductor regions. The impurity concentration of the first semiconductor region is set higher than that of the fourth semiconductor region.

摘要翻译： 提供一种半导体器件，其防止半导体侧壁处的局部击穿的发展，具有稳定的期望的击穿电压。 它包围形成在n型半导体本体的第一主表面上的p型第三半导体区域; 选择性地形成在第二主表面的中心的n型第二半导体区域; 形成在第三和第二半导体区域之间的n型第一半导体区域; 以及围绕第一和第二半导体区域的n型第四半导体区域。 第一半导体区域的杂质浓度被设定为高于第四半导体区域的杂质浓度。

公开(公告)号：US20020072204A1

公开(公告)日：2002-06-13

申请号：US10053570

申请日：2002-01-24

发明人： Toshiya Uemura ,  Naoki Shibata ,  Shizuyo Noiri ,  Masanori Murakami ,  Yasuo Koide ,  Jun Ito

IPC分类号： H01L021/20 ,  H01L021/36 ,  H01L021/265 ,  H01L021/425

CPC分类号： H01L33/42 ,  H01L33/0095 ,  H01L33/32

摘要： A layer comprising cobalt (Co) is formed on a pnull layer by vapor deposition, and a layer comprising gold (Au) is formed thereon. The two layers are alloyed by a heat treatment to form a light-transmitting electrode. The light-transmitting electrode therefore has reduced contact resistance and improved light transmission properties, and gives a light-emitting pattern which is stable over a long time. Furthermore, since cobalt (Co) is an element having a large work function, satisfactory ohmic properties are obtained.

摘要翻译： 通过气相沉积在p +层上形成包含钴（Co）的层，并且在其上形成包含金（Au）的层。 通过热处理将两层合金化以形成透光电极。 因此，透光电极具有降低的接触电阻和改善的透光性，并且给出了长时间稳定的发光图案。 此外，由于钴（Co）是具有大功函数的元素，因此获得令人满意的欧姆特性。

公开(公告)号：US20020064921A1

公开(公告)日：2002-05-30

申请号：US09967928

申请日：2001-10-02

申请人： Hitachi, Ltd.

发明人： Masataka Kato ,  Toshiaki Nishimoto

IPC分类号： H01L021/336 ,  H01L021/425

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531

摘要： In a flash memory having enhanced reliability, each memory cell has a floating gate electrode which is formed on a semiconductor substrate by being interposed by a gate insulation film, a control gate electrode which is formed on the floating gate electrode by being interposed by an inter-layer film, a pair of n-type semiconductor regions (source regions) formed on the semiconductor substrate to confront two sidewise portions of the floating gate electrode, an n-type semiconductor region (drain region) formed beneath the n-type semiconductor region pair by being interposed by channel well regions, and a common p-well formed beneath the semiconductor region. The n-type semiconductor regions and channel well regions make up the DD structure.

摘要翻译： 在具有增强的可靠性的闪速存储器中，每个存储单元具有浮置栅电极，其通过被栅绝缘膜插入在半导体衬底上，控制栅电极通过插入在栅极电极上而形成在控制栅电极上 形成在半导体衬底上的一对n型半导体区域（源极区域），以面对浮置栅电极的两个侧面部分，形成在n型半导体区域下面的n型半导体区域（漏极区域） 由通道阱区域插入，以及形成在半导体区域下方的公共p阱。 n型半导体区域和沟道阱区构成DD结构。

公开(公告)号：US20020050614A1

公开(公告)日：2002-05-02

申请号：US09994277

申请日：2001-11-27

发明人： Sreenath Unnikrishnan

IPC分类号： H01L021/84 ,  H01L027/12 ,  H01L031/0392 ,  H01L021/425

CPC分类号： H01L29/66659 ,  H01L29/1083 ,  H01L29/7835 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78657

摘要： A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node. A contact region of the same conductivity type as the body is formed in the source region with a minimum spacing from the patterned gate corner such that the dopant of the implant region does not diffuse into the gate and thereby destroy the transistor

摘要翻译： 公开了一种硅上氧化物MOS晶体管，其在栅电极的源极侧具有用于与身体节点接触的注入区域。 在源区域中形成与主体相同的导电类型的接触区域，其与图案化的栅极拐角具有最小的间隔，使得注入区域的掺杂剂不扩散到栅极中，从而破坏晶体管

公开(公告)号：US20020025663A1

公开(公告)日：2002-02-28

申请号：US09766844

申请日：2001-01-23

申请人： Mitsubishi Denki Kabushiki Kaisha

发明人： Kenji Yoshiyama ,  Keiichi Higashitani ,  Masao Sugiyama

IPC分类号： H01L021/8238 ,  H01L021/425 ,  H01L021/4763

CPC分类号： H01L21/823842

摘要： There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

摘要翻译： 描述了制造双栅极结构的半导体器件的方法，该方法防止在双栅极结构的栅电极中发生高电阻局部区域。 在隔离氧化膜上形成要成为双栅极结构的栅电极的导电层的多晶硅层。 将N型杂质注入到多晶硅膜的n型注入区域中，同时将光致抗蚀剂膜作为掩模。 将P型杂质注入多晶硅膜3的p型杂质区，同时将另一种光致抗蚀剂膜作为掩模。 进行n型杂质的注入和p型杂质的注入，使得不可避免地形成以这些重叠的方式掺杂这些杂质的重叠区域。

公开(公告)号：US20020025662A1

公开(公告)日：2002-02-28

申请号：US09938527

申请日：2001-08-27

发明人： Satoe Miyata ,  Hiroyuki Umimoto ,  Michikazu Matsumoto ,  Susumu Akamatsu

IPC分类号： H01L021/425

CPC分类号： H01L29/6659 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/7833

摘要： Ions of boron as a dopant are implanted using a gate electrode and an isolation film as a mask, thereby forming an ion-implanted layer as a prototype for an extended heavily doped layer. In this process step, a peak concentration of the dopant existing in the ion-implanted layer is set close to, and equal to or less than, a solid solubility at a process temperature for a first annealing process. Then, almost all of the dopant existing in the extended heavily doped layer is activated by performing the first annealing process. Thereafter, a sidewall and an ion-implanted layer as a prototype for a heavily doped source/drain layer are formed, and then the heavily doped source/drain layer is defined by performing a second RTA process.

摘要翻译： 使用栅电极和隔离膜作为掩模注入硼作为掺杂剂的离子，由此形成离子注入层作为扩展重掺杂层的原型。 在该工序中，将存在于离子注入层中的掺杂剂的峰值浓度设定为在第一退火处理的处理温度下的固体溶解度接近等于或小于固体溶解度。 然后，通过执行第一退火工艺来激活存在于扩展重掺杂层中的几乎全部掺杂剂。 此后，形成作为重掺杂源极/漏极层的原型的侧壁和离子注入层，然后通过执行第二RTA工艺来限定重掺杂的源极/漏极层。