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71.发明授权公开(公告)号：US06894631B1
公开(公告)日：2005-05-17
申请号：US10814661
申请日：2004-03-31
Applicant: Scott Gregory Bardsley
Inventor： Scott Gregory Bardsley
Abstract: An pipeline analog-to-digital converter (ADC) is provided that is capable of applying calibration at a resolution greater than the resolution of a digital output signal provided by the ADC. The ADC includes a calibration component adapted to apply calibration bits to digital output bits generated by stages of the pipeline and corresponding to samples of an analog input signal. The ADC also includes a random number generator that provides at least one random bit having a sub-LSB bit weight. The calibration bits and the at least one random bit are applied as a dither to the digital output bits such that, on average, the digital output signal provided by the ADC is calibrated at a sub-LSB resolution.
Abstract translation: 提供了一种能够以比ADC提供的数字输出信号的分辨率大的分辨率进行校准的流水线模数转换器（ADC）。 ADC包括校准组件，该校准组件适于将校准位应用于由流水线的阶段产生的对应于模拟输入信号的采样的数字输出位。 ADC还包括随机数发生器，其提供至少一个具有子LSB位权重的随机位。 校准位和至少一个随机位作为抖动施加到数字输出位，使得平均来说，由ADC提供的数字输出信号以sub-LSB分辨率进行校准。
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公开(公告)号：US6016113A
公开(公告)日：2000-01-18
申请号：US882826
申请日：1997-06-26
Applicant: Yehuda Binder
Inventor： Yehuda Binder
Abstract: An apparatus for and method of enhancing the accuracy of analog-digital-analog conversions achieves improved accuracy by generating a dither signal which is combined with an input analog signal before the analog input signal is converted to digital form. The combined input analog/dither signal is then converted to digital. The digital signal is then processed or delayed in accordance with the desired function to be performed by the circuit. After digital processing, the digital values are converted back into analog form and the dither signal subsequently removed from the output signal. In addition, an apparatus for and method of enhancing the accuracy of analog-digital-analog conversions that does not utilize an explicit dither signal, utilizes linear interpolation techniques to achieve the effect of a pseudo dither signal. Similarly, time multiplexing techniques are also used to achieve the same effect. The principles of the present invention are applicable in systems that generate analog signals using consecutive digital samples. The resultant output signals from such systems exhibit improved accuracy, lower distortion and higher resolution. The present invention can also be utilized to maintain the original output resolution while requiring fewer bits to represent the digital samples.
Abstract translation: 用于提高模拟数字 - 模拟转换精度的装置和方法通过在将模拟输入信号转换为数字形式之前产生与输入模拟信号组合的抖动信号来实现提高的精度。 然后将组合的输入模拟/抖动信号转换为数字信号。 然后根据要由电路执行的期望功能对数字信号进行处理或延迟。 在数字处理之后，数字值被转换成模拟形式，并且随后从输出信号中去除抖动信号。 此外，用于提高不利用显式抖动信号的模数转换的精度的装置和方法利用线性插值技术来实现伪抖动信号的效果。 类似地，时间复用技术也被用于实现相同的效果。 本发明的原理适用于使用连续的数字采样产生模拟信号的系统。 从这些系统得到的输出信号表现出提高的精度，更低的失真和更高的分辨率。 本发明还可以用于维持原始输出分辨率，同时需要较少的比特来表示数字样本。
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公开(公告)号：US5265039A
公开(公告)日：1993-11-23
申请号：US716752
申请日：1991-06-18
Applicant: Raul Curbelo , Warren R. Howell
Inventor： Raul Curbelo , Warren R. Howell
IPC: H03M1/20
Abstract: A technique for improving the resolution of an A/D converter (30). The input analog signal is sampled to generate an analog level and the analog level is held (20) for an interval. A dither signal (22) is superimposed (23) on the held level to generate a fluctuating voltage. This fluctuating voltage is then sampled (25) a plurality of at least N times, and N sampled values are communicated to the A/D converter (30) so that N digitized values are generated. These digitized values are averaged (32) to provide an output having a digitization error reduced by a factor of up to N.sup.1/2.
Abstract translation: 一种用于提高A / D转换器（30）的分辨率的技术。 输入模拟信号被采样以产生模拟电平，并且模拟电平保持（20）一段间隔。 抖动信号（22）在保持电平上叠加（23）以产生波动电压。 然后对该波动电压进行采样（25）多次至少N次，并且将N个采样值传送到A / D转换器（30），从而生成N个数字化值。 这些数字化值被平均（32），以提供数字化误差降低到N1 / 2的因子的输出。
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74.发明授权Analog-to-digital conversion system as for a narrow bandwidth signal processor 失效模数转换系统，适用于窄带宽信号处理器
公开(公告)号：US4647968A
公开(公告)日：1987-03-03
申请号：US677523
申请日：1984-12-03
Applicant: Donald H. Willis
Inventor： Donald H. Willis
Abstract: A narrow bandwidth analog-to-digital conversion (ADC) system is described in the context of the color burst processing and burst phase detecting circuitry of a digital color television receiver. The ADC includes a dither generator which adds a dither signal to either the analog input signal or to the reference signal used by the ADC. This dither signal increases in magnitude by 1/16 of an LSB value at a rate one-quarter of the burst frequency and changes in sign at one-half of the burst frequency. This signal passes through a low-pass filter in the chrominance channel providing an increase in sample resolution by averaging the samples in a chroma band-pass filter and in the phase detecting circuitry.
Abstract translation: 在数字彩色电视接收机的色同步处理和突发相位检测电路的上下文中描述了窄带宽模数转换（ADC）系统。 ADC包括一个抖动发生器，它将抖动信号添加到模拟输入信号或ADC使用的参考信号。 该抖动信号的幅度以突发频率的四分之一的速率在LSB值上增加1/16，并且在突发频率的一半处以符号改变。 该信号通过色度通道中的低通滤波器，通过对色度带通滤波器和相位检测电路中的采样进行平均来提高样本分辨率。
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公开(公告)号：US4034367A
公开(公告)日：1977-07-05
申请号：US551283
申请日：1975-02-20
Applicant: Takashi Sugiyama , Takashi Tsuda
Inventor： Takashi Sugiyama , Takashi Tsuda
CPC classification number: H03M1/201
Abstract: An analog-to-digital converter arranged to accept an analog input signal and to convert it into an output having digital form. The converter is characterized by a reference random noise source which generates random noise signals with uniform amplitude occurrence probability density in a given range, and by an amplitude comparator arranged to repeatedly compare the amplitude of the random noise signal with the amplitude of a signal varying with the analog signal to be converted. The amplitude comparator supplies output pulses in accordance with the comparisons, e.g., whenever the analog signal amplitude is greater than the random noise amplitude, and the number of pulses from the amplitude comparator in a measurement interval then digitally corresponds to the value of the analog signal and may be utilized, as in a display. Resolution of the converter is increased beyond the minimum amplitude increment of the random noise source signal in one embodiment by superposition on either the analog signal or the random noise signal of a triangular wave with an amplitude greater than the minimum amplitude increment of the random noise signal, and in another embodiment by superposition of a second random noise signal.
Abstract translation: 一种模拟 - 数字转换器，被配置为接受模拟输入信号并将其转换成具有数字形式的输出。 转换器的特征在于参考随机噪声源，其产生在给定范围内具有均匀振幅发生概率密度的随机噪声信号，并且通过幅度比较器布置成重复地比较随机噪声信号的振幅与随 要转换的模拟信号。 幅度比较器根据比较提供输出脉冲，例如，每当模拟信号幅度大于随机噪声幅度时，并且在测量间隔中来自幅度比较器的脉冲数然后数字地对应于模拟信号的值 并且可以如在显示器中那样被利用。 在一个实施例中，转换器的分辨率增加到随机噪声源信号的最小幅度增量之外，通过叠加具有大于随机噪声信号的最小振幅增量的三角波的模拟信号或随机噪声信号 ，并且在另一个实施例中通过叠加第二随机噪声信号。
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Patent Agency Ranking
76.发明公开公开(公告)号：US20240235572A9
公开(公告)日：2024-07-11
申请号：US18490931
申请日：2023-10-20
Inventor： Arindam SANYAL
CPC classification number: H03M1/462 , H03M1/0668 , H03M1/201
Abstract: A low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.
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77.发明公开公开(公告)号：US20230198540A1
公开(公告)日：2023-06-22
申请号：US17555270
申请日：2021-12-17
Applicant: Lawrence Livermore National Security, LLC
Inventor： Brandon Walter Buckley , Ryan Douglas Muir
IPC: H03M1/20
CPC classification number: H03M1/201
Abstract: Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a time-varying dither signal, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein each waveform has a waveform duration, wherein an average of the time-varying dither signal over multiple waveform durations is substantially zero, and wherein the time-varying dither signal varies over each waveform duration, generating a timing alignment, combining each waveform with the corresponding portion of the time-varying dither signal over each waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal, wherein the timing alignment is used to align the multiple instances of the waveform in the analog output signal.
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公开(公告)号：US20190123753A1
公开(公告)日：2019-04-25
申请号：US16164015
申请日：2018-10-18
Applicant: Infineon Technologies AG
Inventor： Dietmar Straeussnigg
CPC classification number: H03M1/201 , H03M1/1245 , H03M1/18 , H03M3/33 , H03M3/468
Abstract: In accordance with an embodiment, a method includes adding a dither signal to a first signal to generate a second signal, subtracting the dither signal from the first signal or subtracting the first signal from the dither signal to generate a third signal, performing a first sigma delta conversion of the second signal to a digital fourth signal, performing a second signal delta conversion of the third signal to a digital fifth signal, combining the digital fourth signal and the digital fifth signal to form a digital sixth signal.
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公开(公告)号：US20190103877A1
公开(公告)日：2019-04-04
申请号：US15722265
申请日：2017-10-02
Applicant: Raytheon Company
Inventor： Ian S. Robinson , Daniel Thompson , James Toplicar
CPC classification number: H03M1/201 , G02B6/3588 , H03M1/0641 , H03M1/12 , H03M1/60 , H03M1/66
Abstract: A method and system for data conversion includes an analog noise generator to generate a random, non-deterministic, analog noise signal. An adder adds the analog noise signal to an analog RF signal to produce a dithered analog signal. A first quantizer converts the analog noise signal to digital to produce a digital noise signal. A second quantizer converts the dithered analog signal to a digital equivalent signal. A digital dither adjustment module removes amplitude measurements of the digital noise signal from the digital equivalent signal to obtain a linearized digital representation of the analog RF signal.
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公开(公告)号：US09806552B2
公开(公告)日：2017-10-31
申请号：US15169981
申请日：2016-06-01
Applicant: Analog Devices Global
Inventor： Paraic Brannick , Colin G. Lyden , Damien J. McCartney , Gabriel Banarie
CPC classification number: H02J7/007 , G04F10/005 , H02J7/345 , H03M1/201 , H03M1/50 , H03M1/52 , H03M1/60
Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.
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