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公开(公告)号：US20240355383A1
公开(公告)日：2024-10-24
申请号：US18637823
申请日：2024-04-17
Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY , THE RESEARCH FOUNDATION FOR THE STATE UNIVERISTY OF NEW YORK
Inventor： Arindam SANYAL , Jae-sun SEO , Vasundhara DAMODARAN , Ziyu LIU
IPC: G11C11/419 , H03M3/00
CPC classification number: G11C11/419 , H03M3/494
Abstract: System and method to improve the linearity of vector matrix multipliers (VMMs) by including (1) delta-sigma modulators that convert the input and output activations into binary pulse trains, (2) charge-domain computation in each SRAM cell that removes the nonlinear dependency on bitline voltage of the result of the multiplication and allows rail-to-rail output swing, and (3) a CMOS switch that transmits input activation to the capacitor in the SRAM cell, which improves linearity by suppressing the switch threshold voltage dependence on input activation voltage.
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2.发明公开公开(公告)号：US20240137040A1
公开(公告)日：2024-04-25
申请号：US18490931
申请日：2023-10-19
Inventor： Arindam SANYAL
CPC classification number: H03M1/462 , H03M1/0668 , H03M1/201
Abstract: A low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.
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3.发明公开公开(公告)号：US20240235572A9
公开(公告)日：2024-07-11
申请号：US18490931
申请日：2023-10-20
Inventor： Arindam SANYAL
CPC classification number: H03M1/462 , H03M1/0668 , H03M1/201
Abstract: A low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.
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