公开(公告)号：US20140114641A1

公开(公告)日：2014-04-24

申请号：US14144830

申请日：2013-12-31

申请人： International Business Machines Corporation

发明人： Shawn D. LUNDVALL ,  Ronald M. SMITH, SR. ,  Phil Chi-Chung YEH

IPC分类号： G06F9/455 ,  H04L9/08

CPC分类号： G06F9/45504 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30094 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/342 ,  G06F21/72 ,  H04L9/08

摘要： A method, system and program product for executing a multi-function instruction in an emulated computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.

摘要翻译： 一种用于在仿真计算机系统中执行多功能指令的方法，系统和程序产品，其通过多功能指令来指定能力查询或执行一个或多个可选功能的选定功能，其中所选功能 是安装的可选功能，其中能力查询确定在计算机系统上安装一个或多个可选功能的哪些可选功能。

公开(公告)号：US20140089599A1

公开(公告)日：2014-03-27

申请号：US13950333

申请日：2013-07-25

申请人： FUJITSU LIMITED

发明人： Hideki OKAWARA

IPC分类号： G06F12/08

CPC分类号： G06F12/0855 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3857 ,  Y02D10/13

摘要： A processor includes a cache write queue configured to store write requests, based on store instructions directed to a cache memory issued by an instruction issuing unit, into entries provided with stream_wait flag, and to output a write request including no stream_wait flag set thereon, from among the stored write requests, to a pipeline operating unit which performs pipeline operation with respect to the cache memory, the cache write queue being further configured to determine, when a stream flag attached to the store instruction is set, that there will be succeeding store instruction directed to a data area same as that accessed by the store instruction, to set the stream_wait flag so as to store the write request into the entry, to merge the write requests based on the store instructions, directed to the same data area, into a single write request, and then to hold the merged write request.

摘要翻译： 处理器包括高速缓存写入队列，其被配置为基于由指令发布单元发出的指向高速缓冲存储器的存储指令将写入请求存储到提供有stream_wait标志的条目中，并且从其中设置不包括其上设置的stream_wait标志的写入请求从 在存储的写入请求中，对于相对于高速缓冲存储器执行流水线操作的流水线操作单元，高速缓存写入队列还被配置为确定在附加到存储指令的流标志被设置时将存在后续的存储 指令指向与存储指令访问的数据区域相同的数据区域，设置stream_wait标志以将写入请求存储到条目中，以将基于指向相同数据区域的存储指令的写入请求合并到 单个写请求，然后保存合并写请求。

公开(公告)号：US20140075159A1

公开(公告)日：2014-03-13

申请号：US13180724

申请日：2011-07-12

申请人： Matteo Frigo ,  Ahmed Gheith ,  Volker Strumpen

发明人： Matteo Frigo ,  Ahmed Gheith ,  Volker Strumpen

IPC分类号： G06F9/38

CPC分类号： G06F9/38 ,  G06F9/30043 ,  G06F9/3009 ,  G06F9/30112 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/4843 ,  G06F11/2094

摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue.

摘要翻译： 公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。 优选实施例定义了用于产生新的上下文切换线程的“fork”和“join”指令。 上下文切换用于隐藏两个存储器访问操作（即，加载和存储）和算术/逻辑操作的延迟。 当在线程中执行的操作引起具有延迟指令流水线的可能性的等待时间时，通过执行到不同线程的上下文切换来隐藏等待时间。 当操作的结果变得可用时，执行回到该线程的上下文切换以允许线程继续。

公开(公告)号：US20140052961A1

公开(公告)日：2014-02-20

申请号：US14000155

申请日：2012-02-17

申请人： Martin Vorbach

发明人： Martin Vorbach

IPC分类号： G06F15/78

CPC分类号： G06F15/7839 ,  G06F8/4441 ,  G06F8/452 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/38 ,  G06F15/7821 ,  G06F2213/0038 ,  G11C8/16 ,  G11C11/412 ,  Y02D10/12 ,  Y02D10/13

摘要： The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.

摘要翻译： 本发明涉及一种多核处理器存储器系统，其中提供了该系统包括多核处理器和系统存储器之间的存储器通道，并且该系统至少包括与处理器核心一样多的存储器通道，每个存储器 专用于处理器核心的通道，并且存储器系统在运行时将动态地专用于访问核心的存储器块相关联，访问内核经由存储器通道具有对存储体的专用访问。

公开(公告)号：US20140047216A1

公开(公告)日：2014-02-13

申请号：US14055194

申请日：2013-10-16

申请人： International Business Machines Corporation

发明人： Michael K. Gschwind ,  Valentina Salapura

IPC分类号： G06F9/30

CPC分类号： G06F9/3005 ,  G06F9/30127 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： Producer-consumer instructions, comprising a first instruction and a second instruction in program order, are fetched requiring in-order execution, the second instruction is modified by the processor so that the first instruction and second instruction can be completed out-of-order, the modification comprising any one of extending an immediate field of the second instruction using immediate field information of the first instruction or providing a source location of the first instruction as an additional source location to source locations of the second instruction.

摘要翻译： 获取需要按顺序执行的第一指令和第二指令的生产者 - 使用者指令，由处理器修改第二指令，使第一指令和第二指令可以按顺序完成， 所述修改包括使用所述第一指令的立即字段信息来扩展所述第二指令的立即字段或者将所述第一指令的源位置作为附加源位置提供给所述第二指令的源位置的任何一个。

公开(公告)号：US20130262839A1

公开(公告)日：2013-10-03

申请号：US13432458

申请日：2012-03-28

申请人： Michael K. Gschwind ,  Valentina Salapura

发明人： Michael K. Gschwind ,  Valentina Salapura

IPC分类号： G06F9/30 ,  G06F9/318

CPC分类号： G06F9/30181 ,  G06F9/3017 ,  G06F9/3836

摘要： A computer system for optimizing instructions is configured to identify two or more machine instructions as being eligible for optimization, to merge the two or more machine instructions into a single optimized internal instruction that is configured to perform functions of the two or more machine instructions, and to execute the single optimized internal instruction to perform the functions of the two or more machine instructions. Being eligible includes determining that the two or more machine instructions include a first instruction specifying a first target register and a second instruction specifying the first target register as a source register and a target register. The second instruction is a next sequential instruction of the first instruction in program order, wherein the first instruction specifies a first function to be performed, and the second instruction specifies a second function to be performed.

摘要翻译： 用于优化指令的计算机系统被配置为将两个或更多个机器指令识别为有资格进行优化，以将两个或多个机器指令合并成被配置为执行两个或更多个机器指令的功能的单个优化内部指令，以及 执行单个优化的内部指令来执行两个或更多个机器指令的功能。 合格包括确定两个或多个机器指令包括指定第一目标寄存器的第一指令和指定第一目标寄存器作为源寄存器和目标寄存器的第二指令。 第二指令是程序顺序中的第一指令的下一个顺序指令，其中第一指令指定要执行的第一功能，并且第二指令指定要执行的第二功能。

公开(公告)号：US20130262822A1

公开(公告)日：2013-10-03

申请号：US13432512

申请日：2012-03-28

申请人： Michael K. Gschwind ,  Valentina Salapura

发明人： Michael K. Gschwind ,  Valentina Salapura

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/3017 ,  G06F9/381 ,  G06F9/384

摘要： Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be executed, detecting a beginning of a first instruction loop in the instructions, determining that a first internal instruction loop corresponding to the first instruction loop is not stored in the loop buffer, fetching the first instruction loop, optimizing one or more instructions corresponding to the first instruction loop to generate a first optimized internal instruction loop, and storing the first optimized internal instruction loop in the loop buffer based on the determination that the first internal instruction loop is not stored in the loop buffer.

摘要翻译： 本发明的实施例涉及一种用于在循环缓冲器中存储内部指令循环的计算机系统。 计算机系统包括循环缓冲器和处理器。 计算机系统被配置为执行一种方法，包括从存储器取出指令以产生要执行的内部指令，检测指令中的第一指令循环的开始，确定与第一指令循环相对应的第一内部指令循环不是 存储在循环缓冲器中，获取第一指令循环，优化与第一指令循环相对应的一个或多个指令以产生第一优化内部指令循环，以及基于确定所述第一优化内部指令循环，将所述第一优化内部指令循环存储在所述循环缓冲器中 第一个内部指令循环不存储在循环缓冲区中。

公开(公告)号：US08533433B2

公开(公告)日：2013-09-10

申请号：US13453075

申请日：2012-04-23

申请人： Oyvind Strom

发明人： Oyvind Strom

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30101 ,  G06F9/30134 ,  G06F9/30174 ,  G06F9/3879

摘要： A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities.

摘要翻译： 用于直接在硬件中执行字节编译的Java程序的微处理器架构。 微处理器面向嵌入式系统领域的下端，并具有两个正交编程模型，即Java模型和RISC模型。 实体共享一个共同的数据路径并独立运行，尽管不是并行的。 微处理器包括一个组合寄存器文件，其中Java模块将寄存器文件中的元素视为循环操作数堆栈，并且RISC模块将元素视为常规寄存器文件。 集成的微处理器架构便于访问靠近硬件的指令，并提供强大的中断和指令捕获功能。

公开(公告)号：US20130212361A1

公开(公告)日：2013-08-15

申请号：US13843576

申请日：2013-03-15

申请人： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

发明人： Michael A. Julier ,  Jeffrey D. Gray ,  Srinivas Chennupaty ,  Sean P. Mirkes ,  Mark P. Seconi

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F7/06 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

摘要： Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

公开(公告)号：US20130151865A1

公开(公告)日：2013-06-13

申请号：US13685953

申请日：2012-11-27

申请人： BLUERISC INC.

发明人： Csaba Andras Moritz ,  Saurabh Chheda ,  Kristopher Carver

IPC分类号： G06F21/12

CPC分类号： G06F21/12 ,  G06F8/41 ,  G06F9/30003 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3846 ,  G06F9/3879 ,  G06F21/55 ,  G06F21/755 ,  G06F2221/033

摘要： A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction. A processor system with a random instruction encoding and randomized execution, providing effective defense against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis.