知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

22 条记录 (耗时 0.018 秒)

    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
    6.
    发明申请
    PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
    具有分支机构错误预测的第二个执行单元的处理程序

    公开(公告)号：US20140195790A1

    公开(公告)日：2014-07-10

    申请号：US13994676

    申请日：2011-12-28

    申请人： Matthew C. Merten ,  Avinash Sodani ,  Sean P. Mirkes ,  Vijaykumar B. Kadgi ,  Bambang Sutanto ,  Chia Yin Kevin Lai ,  Morris Marden ,  Alexandre J. Farcy

    发明人： Matthew C. Merten ,  Avinash Sodani ,  Sean P. Mirkes ,  Vijaykumar B. Kadgi ,  Bambang Sutanto ,  Chia Yin Kevin Lai ,  Morris Marden ,  Alexandre J. Farcy

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

    摘要： A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.

    摘要翻译： 次级跳转执行单元（JEU）并入微处理器以与主JEU同时操作，使得能够执行同时分支操作，并可能检测到多个分支错误预测。 当在同一个指令周期中对两个JEU执行分支操作时，辅助JEU的错误预测处理被划分到主JEU的调度流水线中，使得辅助JEU的分支处理在主JEU的分支处理之后发生，而 初级JEU不处理分支。 此外，在从处理器的重新排序缓冲器接收到nuke命令的情况下，进一步延迟用于辅助JEU的分支处理，以适应主JEU上的nuke的处理。 进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。

    Bit Range Isolation Instructions, Methods, and Apparatus
    8.
    发明申请
    Bit Range Isolation Instructions, Methods, and Apparatus 有权
    位范围隔离说明，方法和设备

    公开(公告)号：US20110153997A1

    公开(公告)日：2011-06-23

    申请号：US12645307

    申请日：2009-12-22

    申请人： Maxim Loktyukhin ,  Eric W. Mahurin ,  Bret L. Toll ,  Martin G. Dixon ,  Sean P. Mirkes ,  David L. Kreitzer ,  El Moustapha Ould-Ahmed-Vall ,  Vinodh Gopal

    发明人： Maxim Loktyukhin ,  Eric W. Mahurin ,  Bret L. Toll ,  Martin G. Dixon ,  Sean P. Mirkes ,  David L. Kreitzer ,  El Moustapha Ould-Ahmed-Vall ,  Vinodh Gopal

    IPC分类号： G06F9/305 ,  G06F9/30 ,  G06F12/02

    CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30094 ,  G06F9/3802

    摘要： Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    摘要翻译： 接收指示源操作数和目标操作数的指令。 将结果存储在目标操作数中以响应指令。 结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。 不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。 还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。

    Bit range isolation instructions, methods, and apparatus
    10.
    发明授权
    Bit range isolation instructions, methods, and apparatus 有权
    位范围隔离指令，方法和设备

    公开(公告)号：US09003170B2

    公开(公告)日：2015-04-07

    申请号：US12645307

    申请日：2009-12-22

    申请人： Maxim Loktyukhin ,  Eric W. Mahurin ,  Bret L. Toll ,  Martin G. Dixon ,  Sean P. Mirkes ,  David L. Kreitzer ,  El Moustapha Ould-Ahmed-Vall ,  Vinodh Gopal

    发明人： Maxim Loktyukhin ,  Eric W. Mahurin ,  Bret L. Toll ,  Martin G. Dixon ,  Sean P. Mirkes ,  David L. Kreitzer ,  El Moustapha Ould-Ahmed-Vall ,  Vinodh Gopal

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00 ,  G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30094 ,  G06F9/3802

    摘要： Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first range of bits having a first end explicitly specified by the instruction in which each bit is identical in value to a bit of the source operand in a corresponding position; and (2) second range of bits that all have a same value regardless of values of bits of the source operand in corresponding positions. Execution of instruction may complete without moving the first range of the result relative to the bits of identical value in the corresponding positions of the source operand, regardless of the location of the first range of bits in the result. Execution units to execute such instructions, computer systems having processors to execute such instructions, and machine-readable medium storing such an instruction are also disclosed.

    摘要翻译： 接收指示源操作数和目标操作数的指令。 将结果存储在目标操作数中以响应指令。 结果操作数可以具有：（1）具有第一端的第一范围，其中每个位在相应位置中的每个位与源操作数的位相同的指令明确地指定; 和（2）与相应位置中的源操作数的位的值无关的所有位都具有相同值的第二范围。 不管移动第一范围的结果相对于源操作数的相应位置中相同值的位，执行指令都可以完成，而不考虑结果中第一个位的位置。 还公开了执行这些指令的执行单元，具有执行这种指令的处理器的计算机系统以及存储这种指令的机器可读介质。