公开(公告)号：US09852087B2

公开(公告)日：2017-12-26

申请号：US12764002

申请日：2010-04-20

Applicant: James B. Williams ,  Shawn Adam Clayton ,  Maria Clara Gutierrez ,  Alexander Nicolson, IV ,  James Winston Smart ,  John Leland Wood ,  David James Duckman ,  Carl John Lindeborg ,  William Irving Leavitt

Inventor： James B. Williams ,  Shawn Adam Clayton ,  Maria Clara Gutierrez ,  Alexander Nicolson, IV ,  James Winston Smart ,  John Leland Wood ,  David James Duckman ,  Carl John Lindeborg ,  William Irving Leavitt

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/16 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

公开(公告)号：US09846655B1

公开(公告)日：2017-12-19

申请号：US14581620

申请日：2014-12-23

Applicant: EMC Corporation

Inventor： Junping Zhao ,  Philippe Armangau ,  Fenghao Zhang ,  Gang Xie

IPC: G06F12/122 ,  G06F13/14 ,  G06F13/00 ,  G06F12/0871 ,  G06F13/16 ,  G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/061 ,  G06F3/0631 ,  G06F12/00 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/123 ,  G06F12/126 ,  G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/161 ,  G06F2212/1024

Abstract: A method is used in managing processing tasks in storage systems. A set of tasks is received for processing. A type of the set of tasks is identified. Based on the type of the set of tasks, a determination is made as to whether to add data objects associated with the set of tasks to a used object list managed in conjunction of a cache of the system for accessing the data objects associated with the set of tasks. The cache is configured to store the data objects of the storage system. A portion of a memory of the storage system is reserved as the cache.

公开(公告)号：US20170358355A1

公开(公告)日：2017-12-14

申请号：US15622383

申请日：2017-06-14

Applicant: CESNET, zajmove sdruzeni pravnickych osob ,  Netcope Technologies, a.s.

Inventor： Viktor PUS ,  Vlastimil KOSAR ,  Jan KORENEK ,  Denis MATOUSEK

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G06F13/16 ,  G06F17/30979

Abstract: The presented connection processes a stream data by a computer. The data is split into blocks called packets and the task is to search for a match of the data in packets with specified patterns—regular expressions, useful in the field of telecommunication technology and services. The connection may be formed within a semiconductor circuit, which serves for receiving, processing, and sending packets. This semiconductor circuit may be implemented by an FPGA-type circuit. In this way, instead of one circuit implementing the automaton with a total data width Sc, a set of simultaneously operating circuits is implemented forming several identical automata at a smaller data width Sn. This eliminates the exponential rise in the number of symbols in the automaton and at the same time it allows achieving a high throughput of the entire connection.

公开(公告)号：US20170358336A1

公开(公告)日：2017-12-14

申请号：US15176442

申请日：2016-06-08

Applicant: Micron Technology, Inc.

Inventor： Taihei Shido

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F13/16 ,  G11C7/10 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/1096

Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.

公开(公告)号：US09842067B2

公开(公告)日：2017-12-12

申请号：US14951023

申请日：2015-11-24

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED

Inventor： David Smith

IPC: G06F3/00 ,  G06F13/10 ,  G06F3/06 ,  G06F13/16 ,  G06F15/167 ,  G06F1/10 ,  G06F5/06 ,  G06F13/42

CPC classification number: G06F13/102 ,  G06F1/10 ,  G06F3/061 ,  G06F3/0614 ,  G06F5/06 ,  G06F13/16 ,  G06F13/423 ,  G06F15/167

Abstract: A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

公开(公告)号：US09823864B2

公开(公告)日：2017-11-21

申请号：US14724510

申请日：2015-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： J. Thomas Pawlowski

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/07 ,  G06F13/16 ,  G11C29/52 ,  H04L12/801 ,  H04L12/825 ,  H04L12/873 ,  H04L1/18 ,  G06F13/38

CPC classification number: G06F3/0619 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0617 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0685 ,  G06F3/0688 ,  G06F11/07 ,  G06F11/0727 ,  G06F11/073 ,  G06F11/076 ,  G06F11/10 ,  G06F11/1016 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F13/16 ,  G06F13/38 ,  G11C29/52 ,  H04L1/189 ,  H04L47/12 ,  H04L47/25 ,  H04L47/52 ,  Y02D10/14

Abstract: A method may include transmitting, via a processor, a plurality of packets to a receiving component, such that the plurality of packets corresponds to a plurality of data operations configured to access a memory component. The plurality of packets is stored in a buffer of the receiving component upon receipt. The method may also include determining, via the processor, whether an available capacity of the buffer is less than a threshold, decreasing a transmission rate of the plurality of packets when the available capacity is less than the threshold.

公开(公告)号：US09817753B2

公开(公告)日：2017-11-14

申请号：US14930641

申请日：2015-11-02

Applicant: International Business Machines Corporation

Inventor： Madhusudanan Kandasamy ,  Randal C. Swanberg

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0611 ,  G06F3/0631 ,  G06F3/0679 ,  G06F12/084 ,  G06F13/16 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/72 ,  G06F2212/7202

Abstract: Disclosed aspects include managing the access of flash memory by a computer system. A physical memory address space which includes a flash memory portion is established. The flash memory portion may correspond to an input/output memory range. An access request may be detected with respect to the physical memory address space. Using a load-store technique to process the access request, the flash memory portion of the physical memory address space may be accessed.

公开(公告)号：US20170323672A1

公开(公告)日：2017-11-09

申请号：US15604251

申请日：2017-05-24

Applicant: Rambus Inc.

Inventor： Ian P. Shaeffer ,  Lei Luo

IPC: G11C7/22 ,  G06F13/40 ,  G06F1/08 ,  G06F13/16 ,  G11C7/10 ,  G06F13/42

CPC classification number: G11C7/22 ,  G06F1/08 ,  G06F13/16 ,  G06F13/4068 ,  G06F13/4243 ,  G11C7/1072

Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

公开(公告)号：US09811453B1

公开(公告)日：2017-11-07

申请号：US13955733

申请日：2013-07-31

Applicant: Juniper Networks, Inc.

Inventor： Srinivas Vaduvatha ,  Deepak Goel ,  Shahriar Ilislamloo

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06

CPC classification number: G06F12/00 ,  G06F3/0659 ,  G06F13/16 ,  G06F13/1631 ,  G06F2212/1016 ,  G06F2212/1024

Abstract: An apparatus includes a scheduler module operatively coupled to each memory block from a set of memory blocks via a shared address bus. The scheduler module is configured to receive a group of memory commands from a set of memory controllers. Each memory controller from the set of memory controllers is uniquely associated with a different memory block from the set of memory blocks. The scheduler module is configured to classify each memory command from the group of memory commands into a category based at least in part on memory commands previously sent to the set of memory blocks via the shared address bus. The scheduler module is configured to select an order in which to send each memory command from the group of memory commands to the set of memory blocks via the shared address bus based at least in part on the category of each memory command.

公开(公告)号：US09804799B2

公开(公告)日：2017-10-31

申请号：US15279169

申请日：2016-09-28

Applicant: SK hynix Inc.

Inventor： Ching-Chung Lai ,  Lian-Chun Lee

IPC: G11C11/34 ,  G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0246 ,  G06F13/16

Abstract: Disclosed are a memory storage device and an operating method thereof. The operating method writes data to a plurality of memory devices of the memory storage device through a controller, and performs interleaving programming on the plurality of memory devices. The operating method includes a write request step, a read request step, a page temporary storage area write step, and a device switching step, which are repeated until the respective memory devices complete the above-described steps and a page temporary storage area programming step. Before the page temporary storage area programming step is performed, data transmitted to page temporary storage areas of the respective memory devices are temporarily stored in the page temporary storage areas. Thus, the number of SRAMs can be, reduced, and a programming operation can be performed on a plurality of memory devices at the same time.