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    Direct memory access controller system with message-based programming
    3.
    发明授权
    Direct memory access controller system with message-based programming 有权
    直接存储器访问控制器系统，具有基于消息的编程

    公开(公告)号：US08108583B2

    公开(公告)日：2012-01-31

    申请号：US11088344

    申请日：2005-03-23

    申请人： Shawn Adam Clayton ,  Brian Mark Fortin ,  Daniel Brian Willie ,  John Leland Wood

    发明人： Shawn Adam Clayton ,  Brian Mark Fortin ,  Daniel Brian Willie ,  John Leland Wood

    IPC分类号： G06F13/36

    CPC分类号： G06F13/28 ,  G06F11/1004

    摘要： A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.

    摘要翻译： 一种数据传输系统，包括第一总线接口，第二总线接口，先进先出存储器，控制器和消息单元。 消息单元可操作用于对来自第一总线接口和第二总线接口的多个数据传送请求消息进行排队。 控制器可操作以处理每个数据传送请求消息并在第一总线接口，先进先出存储器和第二总线接口之间传送数据。 控制器被配置为计算错误检测码（EDC）和链EDC值。

    System and method for regulating message flow in a digital data network
    4.
    发明授权
    System and method for regulating message flow in a digital data network 有权

    公开(公告)号：US07283471B2

    公开(公告)日：2007-10-16

    申请号：US10386642

    申请日：2003-03-11

    申请人： Maria C. Gutierrez ,  Shawn Adam Clayton ,  David R. Follett ,  Harold E. Roman ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  James B. Williams

    发明人： Maria C. Gutierrez ,  Shawn Adam Clayton ,  David R. Follett ,  Harold E. Roman ,  Nitin D. Godiwala ,  Richard F. Prohaska ,  James B. Williams

    IPC分类号： H04L1/00

    CPC分类号： H04L12/5602 ,  H04L47/10 ,  H04L47/16 ,  H04L47/263 ,  H04L47/30 ,  H04L2012/5635 ,  H04L2012/5651 ,  H04L2012/5682 ,  H04Q11/0478

    摘要： A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.

    Shared memory management utilizing a free list of buffer indices
    5.
    发明授权
    Shared memory management utilizing a free list of buffer indices 有权
    共享内存管理利用缓冲索引的空闲列表

    公开(公告)号：US06931497B2

    公开(公告)日：2005-08-16

    申请号：US10340078

    申请日：2003-01-09

    申请人： Shawn Adam Clayton ,  Shaun Andrew McMaster ,  Thomas V. Spencer

    发明人： Shawn Adam Clayton ,  Shaun Andrew McMaster ,  Thomas V. Spencer

    IPC分类号： G06F20060101 ,  G06F9/50 ,  G06F12/00

    CPC分类号： G06F9/5016

    摘要： A method includes receiving a first buffer allocation command from a first processor, the allocation command including a register address associated with a pool of buffers in a shared memory, determining whether a buffer is available in the buffer pool based upon a buffer index corresponding to a free buffer, and if a buffer is determined available allocating the buffer to the first processor.

    摘要翻译： 一种方法包括从第一处理器接收第一缓冲器分配命令，所述分配命令包括与共享存储器中的缓冲器池相关联的寄存器地址，基于与缓冲器索引对应的缓冲器索引来确定缓冲器池中是否可用缓冲器 并且如果缓冲器被确定可用，则将缓冲器分配给第一处理器。

    Virtual peripheral component interconnect multiple-function device
    7.
    发明授权
    Virtual peripheral component interconnect multiple-function device 有权
    虚拟外设组件互连多功能设备

    公开(公告)号：US07107382B2

    公开(公告)日：2006-09-12

    申请号：US10407031

    申请日：2003-04-03

    申请人： Shawn Adam Clayton

    发明人： Shawn Adam Clayton

    IPC分类号： G06F13/00 ,  G06F13/12 ,  H04L29/04 ,  H04L1/00

    CPC分类号： G06F13/385

    摘要： A peripheral component interconnect (PCI) device comprising a bus interface coupled to a component interconnect bus, a plurality of configuration space register sets, and virtual multiple-function logic. Each set of configuration space registers is associated with a function. The virtual multiple-function logic is coupled to the bus interface and the configuration space register sets. The virtual multiple-function logic provides access to a plurality of configuration space registers for a plurality of functions. The virtual multiple-function logic also enables a plurality of functions to share the bus interface and other internal logic.

    摘要翻译： 包括耦合到组件互连总线，多个配置空间寄存器组和虚拟多功能逻辑的总线接口的外围组件互连（PCI）设备。 每组配置空间寄存器与一个功能相关联。 虚拟多功能逻辑耦合到总线接口和配置空间寄存器集合。 虚拟多功能逻辑提供对多个功能的多个配置空间寄存器的访问。 虚拟多功能逻辑还使多个功能能够共享总线接口和其他内部逻辑。