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公开(公告)号：US10269756B2
公开(公告)日：2019-04-23
申请号：US15936075
申请日：2018-03-26
发明人： Cyprian Emeka Uzoh
IPC分类号： H01L23/00 , H01L21/78 , H01L25/00 , H01L21/683 , H01L21/67
摘要： Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.
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公开(公告)号：US09953941B2
公开(公告)日：2018-04-24
申请号：US14835379
申请日：2015-08-25
发明人： Paul M. Enquist
IPC分类号： H01L23/00 , H01L25/065 , H01L25/00 , H01L21/50
CPC分类号： H01L24/09 , H01L21/50 , H01L24/03 , H01L24/80 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/036 , H01L2224/05005 , H01L2224/05078 , H01L2224/05082 , H01L2224/08145 , H01L2224/8019 , H01L2224/80895 , H01L2225/06513
摘要： A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.
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公开(公告)号：US20220319901A1
公开(公告)日：2022-10-06
申请号：US17708688
申请日：2022-03-30
IPC分类号： H01L21/683 , H01L21/78
摘要： A bonding method is disclosed. The method can include directly bonding a first nonconductive bonding material of a semiconductor element to a second nonconductive bonding material of a carrier without an intervening adhesive. The first nonconductive bonding material is disposed on a device portion of the semiconductor element. The second nonconductive bonding material is disposed on a bulk portion of the carrier. A deposited dielectric layer is disposed between the device portion and the bulk portion. The method can include removing the carrier from the semiconductor element by transferring thermal energy to the dielectric layer to induce diffusion of gas out of the dielectric layer.
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公开(公告)号：US20220302058A1
公开(公告)日：2022-09-22
申请号：US17836840
申请日：2022-06-09
发明人： Guilian Gao , Bongsub Lee , Gaius Gillman Fountain, Jr. , Cyprian Emeka Uzoh , Laura Wills Mirkarimi , Belgacem Haba , Rajesh Katkar
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48
摘要： Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.
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公开(公告)号：US20220285303A1
公开(公告)日：2022-09-08
申请号：US17684841
申请日：2022-03-02
IPC分类号： H01L23/00
摘要： A bonded structure is disclosed. The bonded structure can include a first element that includes a first conductive feature and a first nonconductive region. The first conductive feature can include a fine grain metal that has an average grain size of 500 nm or less. The bonded structure can include a second element that includes a second conductive feature and a second nonconductive region. The first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the second nonconductive region is directly bonded to the second nonconductive region without an intervening adhesive.
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76.发明申请公开(公告)号：US20220285236A1
公开(公告)日：2022-09-08
申请号：US17825240
申请日：2022-05-26
IPC分类号： H01L21/66 , H01L21/768 , H01L23/532 , H01L23/538 , H01L23/522
摘要： Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers. Another example process and related layer structure recesses the probe pads to a lower metallization layer and allows recess cavities over the probe pads.
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公开(公告)号：US11417576B2
公开(公告)日：2022-08-16
申请号：US16678058
申请日：2019-11-08
发明人： Rajesh Katkar , Liang Wang , Cyprian Emeka Uzoh , Shaowu Huang , Guilian Gao , Ilyas Mohammed
摘要： Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
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公开(公告)号：US20220254746A1
公开(公告)日：2022-08-11
申请号：US17677161
申请日：2022-02-22
发明人： Paul M. Enquist
IPC分类号： H01L23/00 , H01L21/50 , H01L25/065 , H01L25/00
摘要： A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.
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公开(公告)号：US20220208702A1
公开(公告)日：2022-06-30
申请号：US17564550
申请日：2021-12-29
发明人： Cyprian Emeka Uzoh
IPC分类号： H01L23/00
摘要： An element is disclosed. The element can include a non-conductive structure having a non-conductive bonding surface, a cavity at least partially extending through a portion of a thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed in the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back side opposite the bonding surface. An average size of the grains at the bonding surface is smaller than an average size of the grains adjacent the bottom side of the cavity. The conductive pad can include a crystal structure with grains oriented along a 111 crystal plane. The element can be bonded to another element to form a bonded structure. The element and the other element can be directly bonded to one another without an intervening adhesive.
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公开(公告)号：US20220208650A1
公开(公告)日：2022-06-30
申请号：US17562967
申请日：2021-12-27
IPC分类号： H01L23/48 , H01L21/768
摘要： A microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion that has a first surface and a second surface opposite the first surface. The microelectronic structure can include a via structure that extends at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface. The microelectronic structure can include a first dielectric barrier layer that is disposed on the first surface of the bulk semiconductor portion and extends to the via structure. The microelectronic structure can include a second dielectric layer that is disposed on the first dielectric barrier layer and extends to the via structure.
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