公开(公告)号：US11637126B2

公开(公告)日：2023-04-25

申请号：US17156645

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Sai-Hooi Yeong

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11585 ,  H01L29/51 ,  H01L27/11553 ,  H01L21/28

Abstract: Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.

公开(公告)号：US20230069233A1

公开(公告)日：2023-03-02

申请号：US17460096

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H01L27/11597

Abstract: A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

公开(公告)号：US11574928B2

公开(公告)日：2023-02-07

申请号：US17243732

申请日：2021-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chenchen Jacob Wang ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: H01L27/1159 ,  H01L27/11587 ,  H01L29/417 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor memory structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes spacers formed over opposite sides of the gate structure. The structure also includes source drain epitaxial structures formed on opposite sides of the gate structure beside the spacers. The gate structure includes a III-V ferroelectric layer formed between an interfacial layer and a gate electrode layer.

公开(公告)号：US20220392960A1

公开(公告)日：2022-12-08

申请号：US17876575

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-I Wu ,  Yu-Ming Lin

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes word lines, channel layer, gate dielectric layers, a conductive pillar and a storage pillar. The word lines extend along a first direction over a substrate, and are vertically spaced apart from one another. The channel layers respectively line along a sidewall of one of the word lines. The gate dielectric layers respectively line between one of the word lines and one of the channel layers. The conductive pillar and the storage pillar penetrate through the channel layers. The storage pillar includes an inner electrode, a switching layer and an outer electrode. The switching layer wraps around the inner electrode. The outer electrode laterally surrounds the switching layer, and includes annulus portions vertically spaced apart from one another and each in lateral contact with a corresponding one of the channel layers.

公开(公告)号：US20220384525A1

公开(公告)日：2022-12-01

申请号：US17882845

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-I Wu ,  Yu-Ming Lin

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

公开(公告)号：US20220359386A1

公开(公告)日：2022-11-10

申请号：US17874269

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Wei Li ,  Yu-Ming Lin ,  Mauricio MANFRINI ,  Sai-Hooi Yeong

IPC: H01L23/522 ,  H01L29/78 ,  H01L23/532 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/66

Abstract: A transistor includes a gate, a channel layer, a gate insulation layer, a passivation layer, a liner, a first signal line, and a second signal line. The first signal line is embedded in the passivation layer to form a first via in the passivation layer and overlapping the channel layer. The second signal line is embedded in the passivation layer to form a second via in the passivation layer overlapping the channel layer. The second signal line is in contact with the channel layer. The liner includes an insulation region and a conductive region connected with the insulation region. The insulation region is disposed over the passivation layer and on sidewalls of the first via. The conductive region is disposed under a bottom of the first via and connected with the channel layer. The first signal line is electrically connected with the channel layer through the conductive region.

公开(公告)号：US11488659B2

公开(公告)日：2022-11-01

申请号：US17069312

申请日：2020-10-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Lien-Linus Lu ,  Bo-Feng Young ,  Han-Jong Chia ,  Yu-Ming Lin ,  Sai-Hooi Yeong

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4099 ,  G11C11/4074 ,  G11C5/02

Abstract: A memory circuit includes a memory array and a control circuit. A first column of the memory array includes a select line, first and second bit lines, a first subset of memory cells coupled to the select line and the first bit line, and a second subset of memory cells coupled to the select line and the second bit line. The control circuit is configured to simultaneously activate each of the select line and the first bit line and, during a period in which the select line and first bit line are simultaneously activated, activate a first plurality of word lines, each word line of the first plurality of word lines being coupled to a memory cell of the first subset of memory cells.

公开(公告)号：US20220328502A1

公开(公告)日：2022-10-13

申请号：US17566313

申请日：2021-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ta Yu ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H01L27/1159 ,  H01L27/11597

Abstract: A memory device includes a three dimensional memory array having memory cells arranged on multiple floors in rows and columns. Each column is associated with a bit line and a select line. The memory device further includes select gate pairs each being associated with a column. The bit line of a column is connectable to a corresponding a global bit line through a first select gate of a select gate pair associated with the column and a select line of the column is connectable to a corresponding global select line through the second select gate of the select gate pair associated with the column. The plurality of select gate pairs are formed in a different layer than the plurality of memory cells.

公开(公告)号：US20220285396A1

公开(公告)日：2022-09-08

申请号：US17352339

申请日：2021-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer, Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L23/528 ,  H01L29/78

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

公开(公告)号：US20220278128A1

公开(公告)日：2022-09-01

申请号：US17347596

申请日：2021-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Feng Young ,  Yi-Ching Liu ,  Sai-Hooi Yeong ,  Yih Wang ,  Yu-Ming Lin

IPC: H01L27/11592 ,  H01L23/522 ,  H01L27/11597 ,  G11C11/22

Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.