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159 条记录 (耗时 0.024 秒)

    CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL
    72.
    发明申请
    CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL 有权
    通过使用真空填充材料在高K金属电极结构中去除CAP

    公开(公告)号：US20110129980A1

    公开(公告)日：2011-06-02

    申请号：US12905655

    申请日：2010-10-15

    申请人： Jens Heinrich ,  Frank Seliger ,  Ralf Richter ,  Markus Lenski

    发明人： Jens Heinrich ,  Frank Seliger ,  Ralf Richter ,  Markus Lenski

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/7843

    摘要： Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a protective sidewall spacer structure, which in turn may result in superior uniformity of the threshold voltage of the transistors. The sacrificial fill material may be provided in the form of an organic material that may be reduced in thickness on the basis of a wet developing process, thereby enabling a high degree of process controllability.

    摘要翻译： 可以基于牺牲填充材料有效地去除复杂的高k金属栅极电极结构的介电盖层，从而可靠地保持保护性侧壁间隔结构的完整性，这又可以导致优异的阈值电压均匀性 晶体管。 牺牲填充材料可以以有机材料的形式提供，其可以基于湿式显影工艺而减小厚度，从而能够实现高度的工艺可控性。

    USING HIGH-K DIELECTRICS AS HIGHLY SELECTIVE ETCH STOP MATERIALS IN SEMICONDUCTOR DEVICES
    74.
    发明申请
    USING HIGH-K DIELECTRICS AS HIGHLY SELECTIVE ETCH STOP MATERIALS IN SEMICONDUCTOR DEVICES 有权
    使用高K电介质作为半导体器件中的高选择性止蚀材料

    公开(公告)号：US20110024805A1

    公开(公告)日：2011-02-03

    申请号：US12844135

    申请日：2010-07-27

    申请人： Thorsten Kammler ,  Ralf Richter ,  Markus Lenski ,  Gunter Grasshoff

    发明人： Thorsten Kammler ,  Ralf Richter ,  Markus Lenski ,  Gunter Grasshoff

    IPC分类号： H01L29/40 ,  H01L21/3065 ,  H01L21/266

    CPC分类号： H01L29/4983 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

    摘要： A spacer structure in sophisticated semiconductor devices is formed on the basis of a high-k dielectric material, which provides superior etch resistivity compared to conventionally used silicon dioxide liners. Consequently, a reduced thickness of the etch stop material may nevertheless provide superior etch resistivity, thereby reducing negative effects, such as dopant loss in the drain and source extension regions, creating a pronounced surface topography and the like, as are typically associated with conventional spacer material systems.

    摘要翻译： 在高k电介质材料的基础上形成复杂半导体器件中的间隔结构，其与传统使用的二氧化硅衬垫相比提供了优异的蚀刻电阻率。 因此，蚀刻停止材料的厚度减小可以提供优异的蚀刻电阻率，从而减少负面影响，例如漏极和源极延伸区域中的掺杂剂损失，产生显着的表面形貌等，如通常与常规间隔物相关联 材料系统

    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material
    76.
    发明授权
    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material 有权
    补偿层间电介质材料沉积行为差异的技术

    公开(公告)号：US07785956B2

    公开(公告)日：2010-08-31

    申请号：US12168443

    申请日：2008-07-07

    申请人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    发明人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

    摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    摘要翻译： 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

    Technique for increasing adhesion of metallization layers by providing dummy vias
    78.
    发明授权
    Technique for increasing adhesion of metallization layers by providing dummy vias 有权
    通过提供虚拟通孔增加金属化层附着力的技术

    公开(公告)号：US07611991B2

    公开(公告)日：2009-11-03

    申请号：US11470024

    申请日：2006-09-05

    申请人： Ralf Richter ,  Matthias Schaller ,  Ellen Claus ,  Eckhard Langer

    发明人： Ralf Richter ,  Matthias Schaller ,  Ellen Claus ,  Eckhard Langer

    IPC分类号： H01L21/44

    CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By providing dummy vias below electrically non-functional metal regions, the risk for metal delamination in subsequent processes may be significantly reduced. Moreover, in some embodiments, the mechanical strength of the resulting metallization layers may be even more enhanced by providing dummy metal regions, which may act as anchors for an overlying non-functional metal region. In addition, dummy vias may also be provided in combination with electrically functional metal lines and regions, thereby also enhancing the mechanical stability and the electrical performance thereof.

    摘要翻译： 通过在电气非功能金属区域之下提供虚拟通孔，可以显着降低后续工艺中金属分层的风险。 而且，在一些实施例中，所得到的金属化层的机械强度甚至可以通过提供虚拟金属区域来进一步增强，虚拟金属区域可以用作覆盖的非功能性金属区域的锚点。 此外，还可以与电功能金属线和区域组合提供虚拟通孔，从而也增强机械稳定性及其电性能。