公开(公告)号：US09256246B1

公开(公告)日：2016-02-09

申请号：US14608462

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Yang Du

IPC: H03H11/26 ,  H03K5/12 ,  G06F1/10 ,  H03K5/135 ,  H03K5/00

CPC classification number: G06F1/10 ,  H01L27/0688 ,  H03K5/135 ,  H03K2005/00019

Abstract: Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs) is disclosed. In one aspect, a sensor is placed on each tier of a 3DIC to evaluate a speed characteristic of each tier relative to the speed characteristic of another tier. Based on determining the relative speed characteristics, a control signal may be provided to adjust back body bias elements for clock buffers. Adjusting the back body bias effectively adjusts a threshold voltage of the clock buffers. Adjusting the threshold voltage of the clock buffers has the effect of slowing down or speeding up the clock buffers. For example, slow clock buffers may be sped up by providing a forward body bias and fast clock buffers may be slowed down by providing a reverse body bias. By speeding up slow elements and slowing down fast elements, compensation for the relative speed characteristics may be provided.

Abstract translation: 公开了具有三维（3D）集成电路（IC）（3DIC）中的自适应主体偏置的时钟偏移补偿。 在一个方面，将传感器放置在3DIC的每个层上，以评估每个层相对于另一层的速度特性的速度特性。 基于确定相对速度特性，可以提供控制信号来调整用于时钟缓冲器的背部偏置元件。 调整背面偏置有效地调整时钟缓冲器的阈值电压。 调整时钟缓冲器的阈值电压具有减慢或加速时钟缓冲器的作用。 例如，可以通过提供正向偏置来加速慢时钟缓冲器，并且可以通过提供反向体偏置来减慢快速时钟缓冲器。 通过加快缓慢的元素和减缓快速元素，可以提供相对速度特性的补偿。

公开(公告)号：US09213358B2

公开(公告)日：2015-12-15

申请号：US14159028

申请日：2014-01-20

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: G06F17/50 ,  G06F1/10 ,  H01L27/06

CPC classification number: G06F1/10 ,  G06F17/5031 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/62 ,  G06F2217/84 ,  H01L27/0688

Abstract: Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary embodiment, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay adjustment. In particular, a delay sensing circuit detects a difference in delay at comparable points in the clock tree between different tiers and instructs a programmable delay element to delay the clock signals on the faster of the two tiers. In a second exemplary embodiment, a metal mesh is provided to all elements within the clock tree and acts as a signal aggregator that provides clock signals to the clocked elements substantially simultaneously.

Abstract translation: 公开了单片三维（3D）集成电路（IC）（3DIC）跨层时钟偏移管理系统。 还公开了方法和相关组件。 在示例性实施例中，为了抵消可能在时钟树中的层次之间产生的偏斜，跨层时钟平衡方案​​利用自动延迟调整。 特别地，延迟感测电路检测不同层之间的时钟树中可比较点的延迟差异，并且指示可编程延迟元件在两个层级中更快地延迟时钟信号。 在第二示例性实施例中，金属网格被提供给时钟树中的所有元件，并且用作基本上同时向时钟元件提供时钟信号的信号聚合器。

公开(公告)号：US20150103866A1

公开(公告)日：2015-04-16

申请号：US14091390

申请日：2013-11-27

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Yang Du ,  Mehdi Saeidi

IPC: G01K7/42 ,  G01K1/02

CPC classification number: G01K7/427 ,  G01K1/022 ,  G01K2217/00

Abstract: Embodiments disclosed in the detailed description include digital temperature estimators (DTEs) disposed in integrated circuits (ICs) for estimating temperature within the ICs. Related systems and methods are also disclosed. In one embodiment, the DTEs can be used to estimate temperatures in an IC by implementing a temperature estimation model (TEM). The TEM can provide an estimated temperature of an IC block disposed in the IC based on activity event(s) associated with the IC block, as opposed to providing temperature sensors in the IC to measure temperature of the IC block directly. The DTEs can be operated in real time so that power and/or thermal regulation systems of the IC can obtain accurate and reliable temperature estimation from the DTEs. In this manner, thermal dissipation in the IC may be regulated more effectively.

Abstract translation: 在详细描述中公开的实施例包括设置在用于估计IC内的温度的集成电路（IC）中的数字温度估计器（DTE）。 还公开了相关系统和方法。 在一个实施例中，DTE可用于通过实施温度估计模型（TEM）来估计IC中的温度。 与在IC中提供温度传感器以直接测量IC块的温度相反，TEM可以基于与IC块相关联的活动事件来提供设置在IC中的IC块的估计温度。 DTE可以实时操作，使得IC的功率和/或热调节系统可以从DTE获得准确可靠的温度估计。 以这种方式，可以更有效地调节IC中的散热。

公开(公告)号：US08984463B2

公开(公告)日：2015-03-17

申请号：US13792592

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Yang Du

IPC: G06F17/50 ,  H01L23/522 ,  G11C5/14 ,  G06F1/32

CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

Abstract: The disclosed embodiments comprise a multi-stage circuit operating across different power domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit integrated with a level shifter that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers.

Abstract translation: 所公开的实施例包括跨越不同功率域操作的多级电路。 多级电路可以实现为与电平转换器集成的主从触发器电路，其在不同的电源域之间传送数据。 触发器的主级和从属级可以分为三层3D IC的两层，并且可以包括（i）跨越触发器电路中的不同功率域的电平移位器，（ii）减少的一状态写入延迟 通过自感电源塌陷技术，（iii）使用单片3D IC技术分割不同层级的触发器电源，以及（iv）3D IC层之间的跨功率域数据传输。

公开(公告)号：US20140252306A1

公开(公告)日：2014-09-11

申请号：US13788224

申请日：2013-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： Yang Du

IPC: H01L23/48 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L23/48 ,  B82Y10/00 ,  B82Y99/00 ,  H01L21/76254 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

Abstract: A three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various CMOS transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an oxide layer formed over the regions. Hydrogen ion implantation forms a cleavage interface. The first wafer is flipped and oxide bonded to a second wafer having CMOS devices, and the cleavage interface is thermally activated so that a portion of the lightly doped regions remains bonded to the bottom tier. Nanowire transistors are formed in the top tier layer. The sources and drains for the top tier nanowire transistors are formed by in-situ doping during epitaxial growth. After oxide bonding, the remaining process steps are performed at low temperatures so as not to damage the metal interconnects.

Abstract translation: 一种三维集成电路，包括形成在CMOS晶体管的底层上的顶层纳米线晶体管，具有层间通孔，层内通孔和金属层，以将各种CMOS晶体管和纳米线晶体管连接在一起。 顶层首先作为第一晶片上的轻掺杂区域开始，在该区域上形成氧化物层。 氢离子注入形成裂解界面。 第一晶片被翻转并且氧化物结合到具有CMOS器件的第二晶片，并且裂解界面被热激活，使得一部分轻掺杂区域保持结合到底层。 纳米线晶体管形成在顶层中。 顶层纳米线晶体管的源极和漏极通过在外延生长期间的原位掺杂形成。 在氧化物结合之后，剩余的工艺步骤在低温下进行，以免损坏金属互连。

公开(公告)号：US20140225235A1

公开(公告)日：2014-08-14

申请号：US13765061

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： Yang Du

IPC: H01L23/552 ,  H01L23/373

CPC classification number: H01L23/552 ,  H01L23/373 ,  H01L23/5225 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield is disclosed. In certain embodiments, at least a graphene layer is positioned between two adjacent tiers of the 3DIC. A graphene layer is a sheet like layer made of pure carbon, at least one atom thick with atoms arranged in a regular hexagonal pattern. A graphene layer may be disposed between any number of adjacent tiers in the 3DIC. In exemplary embodiments, the graphene layer provides an electromagnetic interference shield between adjacent tiers or layers in the 3DIC to reduce crosstalk between the tiers. In other exemplary embodiments, the graphene layer(s) can be disposed in the 3DIC to provide a heat sink that directs and dissipates heat to peripheral areas of the 3DIC. In some embodiments, the graphene layer(s) are configured to provide both EMI shielding and heat shielding.

Abstract translation: 公开了一种具有石墨烯屏蔽的三维（3-D）集成电路（3DIC）。 在某些实施例中，至少石墨烯层位于3DIC的两相邻层之间。 石墨烯层是由纯碳制成的片状层，至少一个原子厚度为原子排列成正六边形图案。 石墨烯层可以设置在3DIC中的任意数量的相邻层之间。 在示例性实施例中，石墨烯层在3DIC中的相邻层之间提供电磁干扰屏蔽，以减少层之间的串扰。 在其它示例性实施例中，石墨烯层可以设置在3DIC中，以提供将热量引导和散热到3DIC的周边区域的散热器。 在一些实施例中，石墨烯层被配置为提供EMI屏蔽和热屏蔽。

公开(公告)号：US20140225218A1

公开(公告)日：2014-08-14

申请号：US13765080

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： Yang Du

IPC: H01L21/822 ,  H01L25/065

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/30625 ,  H01L21/82 ,  H01L21/8221 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ion-reduced, ion cut-formed three-dimensional (3D) integrated circuits (IC) (3DICs) are disclosed. Related methods and systems are also disclosed. During an ion-cut process for forming a monolithic 3DIC, extra ions are implanted in the donor wafer to effectuate the ion-cut. Excess, residual implanted ions remain implanted in a top layer of the transfer layer of the 3DIC. However, these residual implanted ions can interfere with operation of electronic components in the 3DIC. In this regard, the 3DIC and methods disclosed herein involve reduction or removal of the residual extra ions before further electronic components are created and layered in a 3DIC. In this manner, the extra charge elements introduced by such extra ions are reduced or removed providing for better functionality in the completed device.

Abstract translation: 公开了离子还原的离子切割形成的三维（3D）集成电路（IC）（3DIC）。 还公开了相关方法和系统。 在用于形成单片3DIC的离子切割工艺期间，在施主晶片中注入额外的离子以实现离子切割。 剩余的注入离子保留注入到3DIC的转移层的顶层中。 然而，这些残留的注入离子可能会干扰3DIC中电子元件的操作。 在这方面，本文公开的3DIC和方法涉及在创建其它电子部件之前还原或去除剩余的额外离子并且在3DIC中分层。 以这种方式，通过这种额外的离子引入的额外的电荷元素被减少或去除，从而在完成的器件中提供更好的功能。

公开(公告)号：US20130299880A1

公开(公告)日：2013-11-14

申请号：US13746011

申请日：2013-01-21

Applicant: QUALCOMM INCORPORATED

Inventor： Yang Du

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L29/66984 ,  H01L43/08 ,  H01L43/12

Abstract: Spin transistors and related memory, memory systems, and methods are disclosed. A spin transistor is provided by at least two magnetic tunnel junctions (MTJs) with a shared multiferroic layer. The multiferroic layer is formed from a piezoelectric (PE) thin film over a ferromagnetic thin film (FM channel) with a metal electrode (metal). The ferromagnetic layer functions as the spin channel and the piezoelectric layer is used for transferring piezoelectric stress to control the spin state of the channel. The MTJ on one side of the shared layer forms a source and the MTJ on the other side is a drain for the spin transistor.

Abstract translation: 公开了旋转晶体管和相关存储器，存储器系统和方法。 自旋晶体管由具有共享多铁层的至少两个磁性隧道结（MTJ）提供。 多铁层由金属电极（金属）的铁磁薄膜（FM通道）上的压电（PE）薄膜形成。 铁磁层用作自旋通道，压电层用于转移压电应力以控制通道的自旋状态。 共享层一侧的MTJ形成源极，另一侧的MTJ是自旋晶体管的漏极。