公开(公告)号：US20160029022A1

公开(公告)日：2016-01-28

申请号：US14806664

申请日：2015-07-23

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Chih-Ming Wang ,  Yung-Chang Chang ,  Chun-Chia Chen ,  Meng-Jye Hu ,  Huei-Min Lin

IPC: H04N19/119 ,  H04N19/91

CPC classification number: H04N19/119 ,  H04N19/157 ,  H04N19/176 ,  H04N19/91 ,  H04N19/96

Abstract: A video processing apparatus includes a first processing circuit, a second processing circuit, and a control circuit. The first processing circuit performs a first processing operation. The second processing circuit performs a second processing operation different from the first processing operation. The control circuit generates at least one output coding unit to the second processing circuit according to an input coding unit generated from the first processing circuit, wherein the control circuit checks a size of the input coding unit to selectively split the input coding unit into a plurality of output coding units.

Abstract translation: 视频处理装置包括第一处理电路，第二处理电路和控制电路。 第一处理电路执行第一处理操作。 第二处理电路执行与第一处理操作不同的第二处理操作。 所述控制电路根据从所述第一处理电路产生的输入编码单元，向所述第二处理电路生成至少一个输出编码单元，其中，所述控制电路检查所述输入编码单元的大小，以选择性地将所述输入编码单元分割成多个 的输出编码单元。

公开(公告)号：US11979593B2

公开(公告)日：2024-05-07

申请号：US17728392

申请日：2022-04-25

Applicant: MEDIATEK INC.

Inventor： Shih-Chun Chiu ,  Tzu-Der Chuang ,  Ching-Yeh Chen ,  Chun-Chia Chen ,  Chih-Wei Hsu ,  Yu-Wen Huang

IPC: H04N7/12 ,  G06T3/02 ,  H04N19/117 ,  H04N19/136 ,  H04N19/139 ,  H04N19/172 ,  H04N19/184 ,  H04N19/463 ,  H04N19/52 ,  H04N19/635 ,  H04N19/82

CPC classification number: H04N19/463 ,  G06T3/02 ,  H04N19/117 ,  H04N19/136 ,  H04N19/139 ,  H04N19/172 ,  H04N19/184 ,  H04N19/52 ,  H04N19/635 ,  H04N19/82

Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m−k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.

公开(公告)号：US11800102B2

公开(公告)日：2023-10-24

申请号：US17552963

申请日：2021-12-16

Applicant: MEDIATEK INC.

Inventor： Chia-Ming Tsai ,  Chun-Chia Chen ,  Chih-Wei Hsu ,  Ching-Yeh Chen ,  Tzu-Der Chuang ,  Yu-Wen Huang

IPC: H04N19/119 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/169 ,  H04N19/159

CPC classification number: H04N19/119 ,  H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/1883

Abstract: Low-latency video coding methods and apparatuses include receiving input data associated with a current Intra slice composed of Coding Tree Units (CTU), where each CTU includes luma and chroma Coding Tree Blocks (CTBs), partitioning each CTB into non-overlapping pipeline units, and encoding or decoding the CTUs in the current Intra slices by performing processing of chroma pipeline units after beginning processing of luma pipeline units in at least one pipeline stage. Each of the pipeline units is processed by one pipeline stage after another pipeline stage, and different pipeline stages process different pipeline units simultaneously. The pipeline stage in the low-latency video coding methods and apparatuses simultaneously processes one luma pipeline unit and at least one previous chroma pipeline unit within one pipeline unit time interval.

公开(公告)号：US11785204B1

公开(公告)日：2023-10-10

申请号：US17842510

申请日：2022-06-16

Applicant: MediaTek Inc.

Inventor： Chen-Yen Lai ,  Tzu-Der Chuang ,  Ching-Yeh Chen ,  Chih-Wei Hsu ,  Chun-Chia Chen ,  Yu-Wen Huang

IPC: H04N19/103 ,  H04N19/154 ,  H04N19/30 ,  H04N19/176 ,  H04N19/12

CPC classification number: H04N19/103 ,  H04N19/12 ,  H04N19/154 ,  H04N19/176 ,  H04N19/30

Abstract: Various schemes for realizing JCCR mode decision in frequency domain are described. An apparatus receives first and second pixel data of a current block of a picture and transform the pixel data into first and second transformed data in frequency domain. The apparatus generates joint pixel data comprising a pixelwise linear combination of the first and second transformed data. The apparatus generates reconstructed joint pixel data based on the joint pixel data by quantization and inverse quantization operations. The apparatus derives first and second reconstructed pixel data based on the reconstructed joint pixel data. The apparatus accordingly calculates first and second distortion values in frequency domain, based on which a preferred mode may be determined to code the current block.

公开(公告)号：US11736704B1

公开(公告)日：2023-08-22

申请号：US17702345

申请日：2022-03-23

Applicant: MEDIATEK INC.

Inventor： Cheng-Yen Chuang ,  Man-Shu Chiang ,  Chun-Chia Chen ,  Chih-Wei Hsu ,  Tzu-Der Chuang ,  Ching-Yeh Chen ,  Yu-Wen Huang

IPC: H04N19/42 ,  H04N19/176 ,  H04N19/159 ,  H04N19/132

CPC classification number: H04N19/42 ,  H04N19/132 ,  H04N19/159 ,  H04N19/176

Abstract: Video encoding methods and apparatuses for Sum of Absolute Transformed Difference (SATD) computation by folded Hadamard transform circuits include splitting a current block into SATD blocks, receiving input data associated with a first block of a first SATD block in a first cycle and receiving input data associated with a second block of the first SATD block in a second cycle, and performing calculations for the first block by shared Hadamard transform circuits in the first cycle and performing calculations for the second block by the shared Hadamard transform circuits in the second cycle. Each shared Hadamard transform circuit is a first part of each folded Hadamard transform circuit. The video encoding methods and apparatuses further perform calculations for the entire SATD block by a final part of each folded Hadamard transform circuit to generate a final SATD result of the first SATD block for encoding.

公开(公告)号：US20230047501A1

公开(公告)日：2023-02-16

申请号：US17874009

申请日：2022-07-26

Applicant: MediaTek Inc.

Inventor： Chih-Yao Chiu ,  Chun-Chia Chen ,  Chih-Wei Hsu ,  Ching-Yeh Chen ,  Tzu-Der Chuang ,  Yu-Wen Huang

IPC: H04N19/105 ,  H04N19/136 ,  H04N19/182 ,  H04N19/176

Abstract: For each prediction candidate of a set of one or more prediction candidates of the current block, a video coder computes a matching cost between a set of reference pixels of the prediction candidate in a reference picture and a set of neighboring pixels of a current block in a current picture. The video coder identifies a subset of the reference pictures as major reference pictures based on a distribution of the prediction candidates among the reference pictures of the current picture. A bounding block is defined for each major reference picture, the bounding block encompassing at least portions of multiple sets of reference pixels for multiple prediction candidates. The video coder assigns an index to each prediction candidate based on the computed matching cost of the set of prediction candidates. A selection of a prediction candidate is signaled by using the assigned index of the selected prediction candidate.

公开(公告)号：US11297348B2

公开(公告)日：2022-04-05

申请号：US16382167

申请日：2019-04-11

Applicant: MediaTek Inc.

Inventor： Man-Shu Chiang ,  Chun-Chia Chen ,  Chih-Wei Hsu

IPC: H04N19/61 ,  H04N19/159 ,  H04N19/137 ,  H04N19/176 ,  H04N19/132 ,  H04N19/196 ,  H04N19/46 ,  H04N19/513 ,  H04N19/52 ,  H04N19/119

Abstract: A video coder that implicitly signals a transform setting for coding a block of pixels is provided. The video coder derives a transform setting for a block of pixels based on a block processing setting. The video coder processes the block of pixels according to the block processing setting. For encoding, the video coder transforms a set of residual pixels to generate a set of transform coefficients according to the transform setting. For decoding, the video coder inverse transforms the transform coefficients to generate a set of residual pixels according to the transform setting.

公开(公告)号：US11240524B2

公开(公告)日：2022-02-01

申请号：US17105569

申请日：2020-11-26

Applicant: MediaTek Inc.

Inventor： Chun-Chia Chen ,  Yu-Ling Hsiao ,  Chih-Wei Hsu ,  Tzu-Der Chuang ,  Ching-Yeh Chen

IPC: H04N19/513 ,  H04N19/70 ,  H04N19/184 ,  H04N19/176

Abstract: A video decoder determines whether the current block is coded by using intra block copy mode. The video decoder identifies a list of one or more prediction candidates for the current block. When the current block is not coded by using intra block copy mode, one or more spatial neighbors of the current block that are positioned in a same MER as the current block are excluded from the list of prediction candidates. When the current block is coded by using intra block copy mode and the list of prediction candidates belongs to a predefined subset of multiple different candidate lists, at least one of the identified prediction candidates is a spatial neighbor of the current block that is positioned in the MER. The video decoder reconstructs the current block by using a prediction candidate selected from the list of prediction candidates to generate a prediction of the current block.

公开(公告)号：US20210329191A1

公开(公告)日：2021-10-21

申请号：US16848858

申请日：2020-04-15

Applicant: MEDIATEK INC.

Inventor： Chun-Chia Chen ,  Chih-Hung Pan ,  Chia-Chi Liu ,  Shun-Fang Liu ,  Meng-Kun Li ,  Chao-An Chen

IPC: H04N5/63 ,  H04N5/44

Abstract: The present invention provides a control method of a receiver. The control method includes the steps of: when the receiver enters a sleep/standby mode, continually detecting an auxiliary signal from an auxiliary channel to generate a detection result; and if the detection result indicates that the auxiliary signal has a preamble or a specific pattern, generating a wake-up control signal to wake up the receiver before successfully receiving the auxiliary signal having a wake-up command.

公开(公告)号：US11115660B2

公开(公告)日：2021-09-07

申请号：US17051276

申请日：2019-04-30

Applicant: MEDIATEK INC.

Inventor： Tzu-Der Chuang ,  Ching-Yeh Chen ,  Kung-Nien Yang ,  Chun-Chia Chen

IPC: H04N19/105 ,  H04N19/119 ,  H04N19/96 ,  H04N19/176 ,  H04N19/186 ,  H04N19/70

Abstract: A methods and apparatus for block partition in video encoding and decoding are disclosed. According to one method, a current data unit is partitioned into initial blocks using inferred splitting without split-syntax signalling. The initial blocks comprises multiple initial luma blocks and multiple initial chroma blocks, and size of the initial luma block is M×N, M and N are positive integers and the current data unit is larger than M×N for the luma component. A partition structure is determined for partitioning each initial luma block and each initial chroma block into one or more luma CUs (coding units) and one or more chroma CUs respectively. The luma syntaxes and the chroma syntaxes associated with one initial block in the current data unit are signalled or parsed, and then the luma syntaxes and the chroma syntaxes associated with one next initial block in the current data unit are signalled or parsed.