公开(公告)号：US10104397B2

公开(公告)日：2018-10-16

申请号：US14716904

申请日：2015-05-20

Applicant: MEDIATEK INC.

Inventor： Meng-Jye Hu ,  Yung-Chang Chang ,  Chia-Yun Cheng

IPC: H04N19/593 ,  H04N19/51 ,  H04N19/55 ,  H04N19/563 ,  H04N19/44 ,  H04N19/423

Abstract: A video processing apparatus includes a reconstruct circuit, a storage device, and an intra prediction circuit. The reconstruct circuit generates reconstructed pixels of a first block of a picture. The storage device at least stores a portion of the reconstructed pixels of the first block, wherein a capacity of the storage device is smaller than a reconstructed data size of the picture. The intra prediction circuit performs intra prediction of a second block of the picture based at least partly on pixel data obtained from the storage device.

公开(公告)号：US20230054524A1

公开(公告)日：2023-02-23

申请号：US17678045

申请日：2022-02-23

Applicant: MEDIATEK INC.

Inventor： Chih-Wen Yang ,  Chi-Hung Chen ,  Kai-Chun Lin ,  Chien-Wei Lin ,  Meng-Jye Hu

IPC: H04N19/423 ,  H04N19/105 ,  H04N19/127 ,  H04N19/156 ,  H04N19/85 ,  H04N19/503 ,  H04N19/593 ,  H04N19/15 ,  H04N19/172

Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

公开(公告)号：US20160029022A1

公开(公告)日：2016-01-28

申请号：US14806664

申请日：2015-07-23

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Chih-Ming Wang ,  Yung-Chang Chang ,  Chun-Chia Chen ,  Meng-Jye Hu ,  Huei-Min Lin

IPC: H04N19/119 ,  H04N19/91

CPC classification number: H04N19/119 ,  H04N19/157 ,  H04N19/176 ,  H04N19/91 ,  H04N19/96

Abstract: A video processing apparatus includes a first processing circuit, a second processing circuit, and a control circuit. The first processing circuit performs a first processing operation. The second processing circuit performs a second processing operation different from the first processing operation. The control circuit generates at least one output coding unit to the second processing circuit according to an input coding unit generated from the first processing circuit, wherein the control circuit checks a size of the input coding unit to selectively split the input coding unit into a plurality of output coding units.

Abstract translation: 视频处理装置包括第一处理电路，第二处理电路和控制电路。 第一处理电路执行第一处理操作。 第二处理电路执行与第一处理操作不同的第二处理操作。 所述控制电路根据从所述第一处理电路产生的输入编码单元，向所述第二处理电路生成至少一个输出编码单元，其中，所述控制电路检查所述输入编码单元的大小，以选择性地将所述输入编码单元分割成多个 的输出编码单元。

公开(公告)号：US11800122B2

公开(公告)日：2023-10-24

申请号：US17678045

申请日：2022-02-23

Applicant: MEDIATEK INC.

Inventor： Chih-Wen Yang ,  Chi-Hung Chen ,  Kai-Chun Lin ,  Chien-Wei Lin ,  Meng-Jye Hu

IPC: H04N19/42 ,  H04N19/423 ,  H04N19/105 ,  H04N19/127 ,  H04N19/156 ,  H04N19/172 ,  H04N19/503 ,  H04N19/593 ,  H04N19/15 ,  H04N19/85

CPC classification number: H04N19/423 ,  H04N19/105 ,  H04N19/127 ,  H04N19/15 ,  H04N19/156 ,  H04N19/172 ,  H04N19/503 ,  H04N19/593 ,  H04N19/85

Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

公开(公告)号：US20150350566A1

公开(公告)日：2015-12-03

申请号：US14722162

申请日：2015-05-27

Applicant: MEDIATEK INC.

Inventor： Meng-Jye Hu ,  Yung-Chang Chang ,  Chia-Yun Cheng

IPC: H04N5/262

CPC classification number: H04N5/2628 ,  H04N19/122 ,  H04N19/136 ,  H04N19/159 ,  H04N19/176 ,  H04N19/70

Abstract: One exemplary video processing apparatus includes a control circuit and a size selection circuit. The control circuit determines picture boundary information. The size selection circuit refers to at least the picture boundary information to select a size for a block associated with encoding of a picture, wherein selection of the size is constrained by the picture boundary information to ensure that the block with the selected size is not across a picture boundary of the picture.

Abstract translation: 一个示例性视频处理设备包括控制电路和尺寸选择电路。 控制电路确定图像边界信息。 尺寸选择电路至少指图像边界信息以选择与图像编码相关联的块的大小，其中尺寸的选择被图像边界信息约束，以确保具有所选尺寸的块不跨越 图片的图片边界。

公开(公告)号：US12063360B2

公开(公告)日：2024-08-13

申请号：US17876567

申请日：2022-07-29

Applicant: MEDIATEK INC.

Inventor： Kai-Chun Lin ,  Chi-Hung Chen ,  Meng-Jye Hu ,  Hsiao-En Chen ,  Chih-Wen Yang ,  Chien-Wei Lin

IPC: H04N19/107 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/503 ,  H04N19/593

CPC classification number: H04N19/107 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/503 ,  H04N19/593

Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.

公开(公告)号：US20230069089A1

公开(公告)日：2023-03-02

申请号：US17837071

申请日：2022-06-10

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Lin ,  Meng-Jye Hu

IPC: H04N19/44 ,  H04N19/176 ,  H04N19/132 ,  H04N19/423 ,  H04N19/593 ,  H04N19/33 ,  H04N19/186 ,  H04N19/127

Abstract: A video decoder has a plurality of processing circuits, including a first processing circuit and a second processing circuit. The first processing circuit applies a first decoding process to a current coding block according to reconstructed neighbor samples, and has a local neighbor buffer for buffering the reconstructed neighbor samples used by the first decoding process. The second processing circuit applies a second decoding process to the current coding block according to at least a portion of the reconstructed neighbor samples retrieved from the local neighbor buffer, wherein the second decoding process is different from the first decoding process.

公开(公告)号：US20230064790A1

公开(公告)日：2023-03-02

申请号：US17876567

申请日：2022-07-29

Applicant: MEDIATEK INC.

Inventor： Kai-Chun Lin ,  Chi-Hung Chen ,  Meng-Jye Hu ,  Hsiao-En Chen ,  Chih-Wen Yang ,  Chien-Wei Lin

IPC: H04N19/107 ,  H04N19/176 ,  H04N19/105 ,  H04N19/423 ,  H04N19/172 ,  H04N19/593 ,  H04N19/159 ,  H04N19/503

Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.

公开(公告)号：US20190075312A1

公开(公告)日：2019-03-07

申请号：US16124170

申请日：2018-09-06

Applicant: MEDIATEK INC.

Inventor： Yung-Chang Chang ,  Chia-Yun Cheng ,  Chih-Ming Wang ,  Meng-Jye Hu ,  Cheng-Han Li

IPC: H04N19/44 ,  H04N19/30 ,  H04N19/68

Abstract: A video decoding method is used for decoding a multi-plane video bitstream. The multi-plane video bitstream includes a first video subset bitstream corresponding to a fundamental plane (FP) and at least one second video subset bitstream corresponding to at least one augmented plane (AP). The video decoding method includes decoding the first video subset bitstream, decoding the at least one second video subset bitstream, and performing resampling of one decoded FP frame to generate one resampled frame. Decoding the first video subset bitstream includes performing decoding of a first FP frame to generate a first decoded FP frame. Decoding the at least one second video subset bitstream includes performing decoding of a first AP frame to generate a first decoded AP frame. A processing time of performing decoding of the first FP frame overlaps a processing time of performing resampling of said one decoded FP frame.

公开(公告)号：US10070070B2

公开(公告)日：2018-09-04

申请号：US14722162

申请日：2015-05-27

Applicant: MEDIATEK INC.

Inventor： Meng-Jye Hu ,  Yung-Chang Chang ,  Chia-Yun Cheng

IPC: H04B1/66 ,  H04N5/262 ,  H04N19/159 ,  H04N19/176 ,  H04N19/70 ,  H04N19/122 ,  H04N19/136

Abstract: One exemplary video processing apparatus includes a control circuit and a size selection circuit. The control circuit determines picture boundary information. The size selection circuit refers to at least the picture boundary information to select a size for a block associated with encoding of a picture, wherein selection of the size is constrained by the picture boundary information to ensure that the block with the selected size is not across a picture boundary of the picture.