公开(公告)号：US12063360B2

公开(公告)日：2024-08-13

申请号：US17876567

申请日：2022-07-29

Applicant: MEDIATEK INC.

Inventor： Kai-Chun Lin ,  Chi-Hung Chen ,  Meng-Jye Hu ,  Hsiao-En Chen ,  Chih-Wen Yang ,  Chien-Wei Lin

IPC: H04N19/107 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/503 ,  H04N19/593

CPC classification number: H04N19/107 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/503 ,  H04N19/593

Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.

公开(公告)号：US20230064790A1

公开(公告)日：2023-03-02

申请号：US17876567

申请日：2022-07-29

Applicant: MEDIATEK INC.

Inventor： Kai-Chun Lin ,  Chi-Hung Chen ,  Meng-Jye Hu ,  Hsiao-En Chen ,  Chih-Wen Yang ,  Chien-Wei Lin

IPC: H04N19/107 ,  H04N19/176 ,  H04N19/105 ,  H04N19/423 ,  H04N19/172 ,  H04N19/593 ,  H04N19/159 ,  H04N19/503

Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.

公开(公告)号：US10939102B2

公开(公告)日：2021-03-02

申请号：US16666380

申请日：2019-10-28

Applicant: MEDIATEK INC.

Inventor： Yung-Chang Chang ,  Chih-Ming Wang ,  Chia-Yun Cheng ,  Chi-Hung Chen ,  Kai-Chun Lin ,  Chih-Wen Yang ,  Hsuan-Wen Peng

IPC: H04N19/117 ,  H04N19/82 ,  H04N19/182 ,  H04N19/176

Abstract: A post processing apparatus includes a super-resolution (SR) filtering circuit and a loop restoration (LR) filtering circuit. The SR filtering circuit applies SR filtering to a processing result of a preceding circuit. The LR filtering circuit applies LR filtering to a processing result of the SR filtering circuit. Before the SR filtering circuit finishes SR filtering of all pixels of a frame that are generated by the preceding circuit, the LR filtering circuit starts LR filtering of pixels that are derived from applying SR filtering to pixels included in the frame.

公开(公告)号：US11800122B2

公开(公告)日：2023-10-24

申请号：US17678045

申请日：2022-02-23

Applicant: MEDIATEK INC.

Inventor： Chih-Wen Yang ,  Chi-Hung Chen ,  Kai-Chun Lin ,  Chien-Wei Lin ,  Meng-Jye Hu

IPC: H04N19/42 ,  H04N19/423 ,  H04N19/105 ,  H04N19/127 ,  H04N19/156 ,  H04N19/172 ,  H04N19/503 ,  H04N19/593 ,  H04N19/15 ,  H04N19/85

CPC classification number: H04N19/423 ,  H04N19/105 ,  H04N19/127 ,  H04N19/15 ,  H04N19/156 ,  H04N19/172 ,  H04N19/503 ,  H04N19/593 ,  H04N19/85

Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

公开(公告)号：US20230021722A1

公开(公告)日：2023-01-26

申请号：US17586742

申请日：2022-01-27

Applicant: MEDIATEK INC.

Inventor： Kai-Chun Lin ,  Sheng-Jen Wang ,  Chi-Hung Chen

IPC: H04N19/137 ,  H04N19/105 ,  H04N19/80 ,  H04N19/176

Abstract: A motion vector refinement apparatus includes a storage device, a reference block fetch circuit, and a processing circuit. The reference block fetch circuit fetches a forward reference block and a backward reference block according to at least specified motion vectors (MVs) of a current block, and stores the forward reference block and the backward reference block into the storage device. The processing circuit derives a first reference block from the forward reference block and a second reference block from the backward reference block, calculates at least one accumulated pixel difference (APD) value for at least one block pair each having a first block found in the first reference block and a second block found in the second reference block, and determines an offset setting for motion vector refinement of the specified MVs according to the at least one APD value.

公开(公告)号：US20230054524A1

公开(公告)日：2023-02-23

申请号：US17678045

申请日：2022-02-23

Applicant: MEDIATEK INC.

Inventor： Chih-Wen Yang ,  Chi-Hung Chen ,  Kai-Chun Lin ,  Chien-Wei Lin ,  Meng-Jye Hu

IPC: H04N19/423 ,  H04N19/105 ,  H04N19/127 ,  H04N19/156 ,  H04N19/85 ,  H04N19/503 ,  H04N19/593 ,  H04N19/15 ,  H04N19/172

Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.