公开(公告)号：US09130158B1

公开(公告)日：2015-09-08

申请号：US14325911

申请日：2014-07-08

Applicant: Lam Research Corporation

Inventor： Meihua Shen ,  Harmeet Singh ,  Samantha S. H. Tan ,  Jeffrey Marks ,  Thorsten Lill ,  Richard P. Janek ,  Wenbing Yang ,  Prithu Sharma

IPC: H01L21/00 ,  H01L43/12 ,  H01L21/02

CPC classification number: H01L43/12 ,  C23F1/08 ,  C23F1/12 ,  C23F4/00 ,  H01L21/02554 ,  H01L27/228 ,  H01L43/02 ,  H01L43/10 ,  H01L45/1675

Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds. A desorption of the volatile organometallic compounds is performed.

Abstract translation: 提供一种用于在一个或多个循环中用至少一个金属层蚀刻堆叠的方法。 进行引发步骤，将至少一个金属层的一部分转化为金属氧化物，金属卤化物或晶格损坏的金属部位。 执行反应性步骤提供一个或多个循环，其中每个循环包括提供有机溶剂蒸气以形成溶剂化金属，金属卤化物或金属氧化物状态，并提供有机配体溶剂以形成挥发性有机金属化合物。 进行挥发性有机金属化合物的解吸。

公开(公告)号：US20150249016A1

公开(公告)日：2015-09-03

申请号：US14337953

申请日：2014-07-22

Applicant: Lam Research Corporation

Inventor： Monica Titus ,  Gowri Kamarthy ,  Harmeet Singh ,  Yoshie Kimura ,  Meihua Shen ,  Baosuo Zhou ,  Yifeng Zhou ,  John Hoang

IPC: H01L21/3065 ,  H01L21/66 ,  H01L21/67 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L22/12 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67103 ,  H01L22/20

Abstract: A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

Abstract translation: 在等离子体蚀刻室中平坦化半导体衬底的上表面的方法包括将衬底支撑在衬底支撑组件的支撑表面上，该衬底支撑组件包括其中独立控制的热控元件的阵列，其可操作以控制空间和时间温度 的基板支撑组件的支撑表面以形成独立可控的加热器区域，其形成为对应于横跨半导体基板的上表面的期望温度分布。 在等离子体蚀刻期间跨越半导体衬底的上表面的蚀刻速率取决于其局部温度，其中确定期望的温度分布，使得半导体衬底的上表面在预定时间内被平坦化。 将衬底等离子体蚀刻预定时间，从而平坦化衬底的上表面。

公开(公告)号：US20150181683A1

公开(公告)日：2015-06-25

申请号：US14136826

申请日：2013-12-20

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Christopher Kimball ,  Keith Gaff ,  Tyler Gloski

IPC: H05F3/02 ,  H01L21/683

CPC classification number: H01L21/6833

Abstract: A semiconductor wafer processing apparatus for processing semiconductor wafers comprises a semiconductor wafer processing chamber in which a semiconductor wafer is processed, a process gas source in fluid communication with the processing chamber adapted to supply process gas into the processing chamber, a vacuum source adapted to exhaust process gas and byproducts of the processing from the processing chamber, and an electrostatic chuck assembly. The electrostatic chuck assembly comprises a support surface in a layer of ceramic material on which the semiconductor wafer is supported during processing of the wafer in the chamber, at least one electrostatic clamping electrode embedded in the layer of ceramic material, the at least one electrostatic clamping electrode operable to apply an electrostatic clamping force to the wafer on the support surface when an electrostatic clamping voltage is applied to the clamping electrode, and at least one declamping electrode embedded in the layer of ceramic material above the at least one electrostatic clamping electrode operable to provide a path for draining any residual charge between the wafer and the support surface when the electrostatic clamping voltage is no longer applied to the clamping electrode.

Abstract translation: 一种用于处理半导体晶片的半导体晶片处理装置，包括处理半导体晶片的半导体晶片处理室，与处理室流体连通的处理气体源，其适于将处理气体供应到处理室中，适于排出的真空源 来自处理室的处理气体和副产物以及静电吸盘组件。 静电卡盘组件包括在陶瓷材料层中的支撑表面，其中半导体晶片在腔室中的晶片处理期间被支撑，至少一个静电夹持电极嵌入在陶瓷材料层中，该至少一个静电夹持 电极，其可操作以当静电钳位电压施加到所述夹持电极时将静电夹持力施加到所述支撑表面上的所述晶片;以及至少一个在所述至少一个静电夹持电极上方的陶瓷材料层中的所述电极， 当静电钳位电压不再施加到夹紧电极时，提供用于在晶片和支撑表面之间排出任何残留电荷的路径。

公开(公告)号：US09018103B2

公开(公告)日：2015-04-28

申请号：US14038388

申请日：2013-09-26

Applicant: Lam Research Corporation

Inventor： Joydeep Guha ,  Sirish K. Reddy ,  Kaushik Chattopadhyay ,  Thomas W. Mountsier ,  Aaron Eppler ,  Thorsten Lill ,  Vahid Vahedi ,  Harmeet Singh

IPC: H01L21/302 ,  H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11556

Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.

Abstract translation: 提供了一种用于蚀刻堆叠中的特征的方法。 通过在堆叠上形成包含碳或氧化硅的第一硬掩模层形成组合硬掩模，在第一硬掩模层上形成包含金属的第二硬掩模层，以及对第一和第二硬掩模层进行构图。 堆叠通过组合硬掩模进行蚀刻。

公开(公告)号：US20150048740A1

公开(公告)日：2015-02-19

申请号：US14466724

申请日：2014-08-22

Applicant: Lam Research Corporation

Inventor： John C. Valcore, JR. ,  Harmeet Singh ,  Bradford J. Lyndaker

IPC: H01J37/32 ,  H03L7/00

CPC classification number: H01J37/32146 ,  H01J37/32082 ,  H01J37/32174 ,  H01J37/32183 ,  H01J37/3244 ,  H01J37/3255 ,  H01J2237/327 ,  H03K3/01 ,  H03L7/00 ,  H03L7/06 ,  H05H2001/4682

Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.

Abstract translation: 描述了在一个状态下实现子脉冲的方法。 该方法包括从时钟源接收时钟信号，时钟信号具有两个状态，并从时钟信号产生脉冲信号。 脉冲信号在状态之一内具有子状态。 子状态相对于彼此以大于状态频率的频率交替。 该方法包括提供脉冲信号以控制由RF发生器产生的射频（RF）信号的功率。 功率被控制为与脉冲信号同步。

公开(公告)号：US20150028744A1

公开(公告)日：2015-01-29

申请号：US14317360

申请日：2014-06-27

Applicant: Lam Research Corporation

Inventor： John C. Valcore, JR. ,  Harmeet Singh ,  Henry Povolny

IPC: H01J37/32

CPC classification number: H01J37/32926 ,  G05B19/418 ,  H01J37/32183 ,  H01J37/32935 ,  H01J37/3299

Abstract: A method for performing chamber-to-chamber matching includes receiving a voltage and a current measured at an output of an RF generator of a first plasma system. The method further includes calculating a sum of terms. The first term is a first product of a coefficient and a function of the voltage. The second term is a second product of a coefficient and a function of the current. The third term is a third product of a coefficient, a function of the voltage, and a function of the current. The method further includes determining the sum to be the etch rate associated with the first plasma system and adjusting power output from an RF generator of a second plasma system to achieve the etch rate associated with the first plasma system.

Abstract translation: 用于执行室到室匹配的方法包括接收在第一等离子体系统的RF发生器的输出处测量的电压和电流。 该方法还包括计算项的和。 第一项是系数和电压函数的第一个乘积。 第二项是当前系数和函数的第二个乘积。 第三项是系数的第三乘积，电压的函数和电流的函数。 该方法还包括将该和确定为与第一等离子体系统相关联的蚀刻速率，并调整从第二等离子体系统的RF发生器输出的功率，以实现与第一等离子体系统相关联的蚀刻速率。

公开(公告)号：US20140357092A1

公开(公告)日：2014-12-04

申请号：US13909349

申请日：2013-06-04

Applicant: Lam Research Corporation

Inventor： Harmeet Singh

IPC: H01L21/67 ,  H01L21/268

CPC classification number: H01L21/268 ,  H01J37/321 ,  H01J37/32486 ,  H01J37/32495 ,  Y10T137/0318

Abstract: A semiconductor plasma processing apparatus includes a vacuum chamber in which semiconductor substrates are processed, a process gas source in fluid communication with the vacuum chamber for supplying a process gas into the vacuum chamber, and an RF energy source adapted to energize the process gas into the plasma state in the vacuum chamber. The apparatus can also include a chamber wall wherein the chamber wall includes a means for supplying a plasma compatible liquid to a plasma exposed surface thereof wherein the plasma compatible liquid flows over the plasma exposed surface thereby forming a flowing protective liquid layer thereon. A liquid supply delivers the plasma compatible liquid to the chamber wall.

Abstract translation: 半导体等离子体处理装置包括：真空室，其中处理半导体基板;与真空室流体连通的处理气体源，用于将工艺气体供应到真空室中，以及RF能量源，其适于将处理气体激励到 真空室中的等离子体状态。 该装置还可以包括室壁，其中室壁包括用于将等离子体相容液体供应到等离子体暴露表面的装置，其中等离子体相容的液体在等离子体暴露表面上流动，从而在其上形成流动的保护液体层。 液体供应器将等离子体相容的液体输送到室壁。

公开(公告)号：US20140335698A1

公开(公告)日：2014-11-13

申请号：US13888754

申请日：2013-05-07

Applicant: LAM RESEARCH CORPORATION

Inventor： Harmeet Singh ,  Thorsten Lill

IPC: H01J37/32 ,  H01L21/48 ,  H01L21/02

CPC classification number: H01J37/32495 ,  C23C16/4404 ,  H01J37/32477 ,  H01J37/32715 ,  H01J37/32724 ,  H01J2237/0203 ,  H01J2237/332 ,  H01J2237/334 ,  H01J2237/3344 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/6715 ,  H01L21/68735

Abstract: A component of a plasma processing chamber having a protective liquid layer on a plasma exposed surface of the component. The protective liquid layer can be replenished by supplying a liquid to a liquid channel and delivering the liquid through liquid feed passages in the component. The component can be an edge ring which surrounds a semiconductor substrate supported on a substrate support in a plasma processing apparatus wherein plasma is generated and used to process the semiconductor substrate. Alternatively, the protective liquid layer can be cured or cooled sufficiently to form a solid protective layer.

Abstract translation: 等离子体处理室的组件，其在组件的等离子体暴露表面上具有保护液层。 可以通过向液体通道供应液体并通过液体供给通道将液体输送到部件中来补充保护液体层。 该组件可以是围绕在等离子体处理装置中的支撑在基板支撑件上的半导体衬底的边缘环，其中产生等离子体并用于处理半导体衬底。 或者，可以将保护液层充分固化或冷却以形成固体保护层。

公开(公告)号：US20140263274A1

公开(公告)日：2014-09-18

申请号：US14290542

申请日：2014-05-29

Applicant: Lam Research Corporation

Inventor： Harmeet Singh

IPC: H05B1/02 ,  H01L21/67

CPC classification number: H05B1/0233 ,  H01L21/67109 ,  H01L21/67288

Abstract: Described herein is a method of detecting fault conditions in a multiplexed multi-heater-zone heating plate for a substrate support assembly used to support a semiconductor substrate in a semiconductor processing apparatus.

Abstract translation: 这里描述了一种检测用于在半导体处理装置中支撑半导体衬底的衬底支撑组件的多路复用多加热器区域加热板中的故障状况的方法。

公开(公告)号：US08680441B2

公开(公告)日：2014-03-25

申请号：US14013447

申请日：2013-08-29

Applicant: Lam Research Corporation

Inventor： Harmeet Singh

IPC: H05B3/26 ,  F27B5/14 ,  F27D11/02 ,  H01L23/28 ,  H01L23/52

CPC classification number: H01L21/3065 ,  B29D7/01 ,  H01C17/28 ,  H01L21/67109 ,  H01L21/67248 ,  H01L21/6831 ,  H05B3/68 ,  H05B2203/037

Abstract: A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar heater zone includes one or more heater element made of an insulator-conductor composite. A substrate support assembly in which the heating plate is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the heating plate include bonding together ceramic having planar heater zones, power supply lines, power return lines and vias.

Abstract translation: 一种用于半导体等离子体处理设备中的基板支撑组件的加热板，包括以可伸缩复用布局布置的多个可独立控制的平面加热器区域，以及用于独立地控制和供电平面加热器区域的电子装置。 每个平面加热器区域包括由绝缘体 - 导体复合材料制成的一个或多个加热元件。 其中结合加热板的基板支撑组件包括静电夹持电极和温度控制的基板。 制造加热板的方法包括将具有平面加热区，电源线，功率返回线和通孔的陶瓷结合在一起。