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    DOUBLE SELF ALIGNED VIA PATTERNING
    71.
    发明申请
    DOUBLE SELF ALIGNED VIA PATTERNING 有权
    双向自对准通过方式

    公开(公告)号：US20150371896A1

    公开(公告)日：2015-12-24

    申请号：US14837827

    申请日：2015-08-27

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Yunpeng Yin ,  Ailian Zhao

    IPC: H01L21/768

    CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898

    Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

    Abstract translation: 一种包括在衬底上形成五层硬掩模的方法，所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中，产生第一通孔图案，第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在 双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中，从而产生自对准的通孔，所述自对准通孔开口通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。

    WORK FUNCTION METAL FILL FOR REPLACEMENT GATE FIN FIELD EFFECT TRANSISTOR PROCESS
    72.
    发明申请
    WORK FUNCTION METAL FILL FOR REPLACEMENT GATE FIN FIELD EFFECT TRANSISTOR PROCESS 有权
    工作功能用于更换栅极金属场效应晶体管工艺的金属填料

    公开(公告)号：US20150236159A1

    公开(公告)日：2015-08-20

    申请号：US14184229

    申请日：2014-02-19

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

    IPC: H01L29/78 ,  H01L21/306 ,  H01L29/49 ,  H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L21/308

    CPC classification number: H01L29/66795 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/28088 ,  H01L21/31122 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

    Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

    Abstract translation: 一种形成半导体器件的方法，包括在鳍结构的沟道部分上形成牺牲栅极结构，其中牺牲栅极结构的侧壁与鳍结构的沟道部分的上表面的交点处的角度为 钝。 外延源极和漏极区结构形成在鳍结构的源极区域和漏极区域部分上。 在牺牲栅极结构的侧壁上形成至少一种电介质材料。 可以去除牺牲栅极结构以为鳍结构的通道部分提供开口。 在开口中形成功能门结构。 由功能门结构的侧壁与翅片结构的通道部分的上表面的交点限定的至少一个角度是钝的。

    Svia using a single damascene interconnect
    76.
    发明授权
    Svia using a single damascene interconnect 有权

    公开(公告)号：US11037822B2

    公开(公告)日：2021-06-15

    申请号：US16406447

    申请日：2019-05-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Yann Mignot ,  Muthumanickam Sankarapandian ,  Yongan Xu ,  Joe Lee

    IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L21/321

    Abstract: A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.

    Extreme ultraviolet lithography patterning with directional deposition
    78.
    发明授权
    Extreme ultraviolet lithography patterning with directional deposition 有权

    公开(公告)号：US10957552B2

    公开(公告)日：2021-03-23

    申请号：US16666948

    申请日：2019-10-29

    Applicant: International Business Machines Corporation

    Inventor： Yongan Xu ,  Ekmini Anuja De Silva ,  Su Chen Fan ,  Yann Mignot

    IPC: H01L21/308 ,  G03F1/22 ,  H01L21/033

    Abstract: Semiconductor structures fabricated via extreme ultraviolet (EUV) lithographic patterning techniques implementing directional deposition on a EUV resist mask improves selectivity and critical dimension control during the patterning of features in multiple layers of the semiconductor substrate. A semiconductor structure includes a substrate structure having an extreme ultraviolet resist mask disposed over one or more additional layers of the substrate structure. The extreme ultraviolet resist mask defines patterning features. A hard mask layer including a hard mask material is disposed on the extreme ultraviolet resist mask and covers the patterning features of the extreme ultraviolet resist mask.

    Method and structure for cost effective enhanced self-aligned contacts
    80.
    发明授权
    Method and structure for cost effective enhanced self-aligned contacts 有权

    公开(公告)号：US10818548B1

    公开(公告)日：2020-10-27

    申请号：US16426199

    申请日：2019-05-30

    Applicant: International Business Machines Corporation

    Inventor： Kafai Lai ,  Chih-Chao Yang ,  Yongan Xu ,  Su Chen Fan

    IPC: H01L21/768 ,  H01L29/417 ,  H01L21/3213 ,  H01L27/088

    Abstract: Various semiconductor fabrication methods and structures are disclosed for cost effectively fabricating a self-aligned contact. A source-drain active region is on a substrate and horizontally extends to sidewall spacers of two adjacent gate stacks on the substrate. A conductive material layer including Titanium is formed by selective deposition on the source-drain active area. An interlevel dielectric (ILD) layer is deposited over the source-drain active area and the two gate stacks. Vertical directional etching in the ILD layer forms a vertical trench contacting the conductive material layer. Selective wet etching in the vertical trench selectively etches the conductive material layer and forms a void therein. Deposition of a second conductive material in the vertical trench fills the vertical trench, including the void, and the second conductive material contacts the top surface of the source-drain active area to form a source-drain self-aligned contact.

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