公开(公告)号：US20140363959A1

公开(公告)日：2014-12-11

申请号：US14308095

申请日：2014-06-18

申请人： HYUNDAI MOTOR COMPANY

发明人： Kyoung Kook Hong ,  Jong Seok Lee

IPC分类号： H01L29/872 ,  H01L21/02 ,  H01L21/265 ,  H01L29/16

CPC分类号： H01L29/872 ,  H01L21/02529 ,  H01L21/26506 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/66143

摘要： The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n− epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n− epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n− epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer.

摘要翻译： 本发明提供一种碳化硅肖特基势垒二极管器件及其制造方法。 碳化硅肖特基二极体装置包括初级n外延层，n +外延区和肖特基金属层。 主n外延层沉积在与欧姆金属层的下表面连接的n +衬底上。 通过将n +离子注入初级n外延层的中心区域来形成n +外延区域。 肖特基金属层沉积在n +外延层上。

公开(公告)号：US08772112B1

公开(公告)日：2014-07-08

申请号：US13830260

申请日：2013-03-14

申请人： Hyundai Motor Company

发明人： Dae Hwan Chun ,  Jong Seok Lee ,  Kyoung-Kook Hong ,  Youngkyun Jung

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/0634 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： Disclosed is a method for fabricating a semiconductor device including: sequentially forming a first insulating film and a first barrier layer on a first surface of a substrate; etching the first barrier layer to form a first barrier layer pattern; etching the first insulating film to form a first insulating film pattern; removing the first barrier layer pattern and forming a first type epitaxial layer on an exposed first portion of the substrate; forming a second insulating film and a second barrier layer on the first type epitaxial layer and the first insulating film pattern; etching the second barrier layer to form a second barrier layer pattern; etching the second insulating film to form a second insulating film pattern, and etching the first insulating film pattern; and forming a second type epitaxial layer on an exposed second portion of the first surface of the n substrate.

摘要翻译： 公开了一种制造半导体器件的方法，包括：在衬底的第一表面上依次形成第一绝缘膜和第一阻挡层; 蚀刻第一阻挡层以形成第一阻挡层图案; 蚀刻第一绝缘膜以形成第一绝缘膜图案; 去除所述第一阻挡层图案并在所述基板的暴露的第一部分上形成第一类型的外延层; 在所述第一型外延层和所述第一绝缘膜图案上形成第二绝缘膜和第二阻挡层; 蚀刻所述第二阻挡层以形成第二阻挡层图案; 蚀刻第二绝缘膜以形成第二绝缘膜图案，并蚀刻第一绝缘膜图案; 以及在所述n基板的所述第一表面的暴露的第二部分上形成第二类型的外延层。

公开(公告)号：US12101463B2

公开(公告)日：2024-09-24

申请号：US17440567

申请日：2020-03-20

申请人： Hyundai Motor Company ,  Kia Motors Corporation ,  Kwangwoon University Industry-Academic Collaboration Foundation

发明人： Dong Gyu Sim ,  Sea Nae Park ,  Jong Seok Lee ,  Seung Wook Park ,  Wha Pyeong Lim

IPC分类号： H04N19/105 ,  H04N19/132 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

CPC分类号： H04N19/105 ,  H04N19/132 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

摘要： The present embodiment, for an intra prediction method used by an intra prediction device, provides the method comprising: decoding, from a bitstream, mode information indicating use of a prediction derivation mode for a prediction mode block; deriving an intra prediction mode of each pixel group from intra prediction modes of pre-reconstructed reference pixels at a plurality of positions near the prediction mode block for each pixel group including one or more pixels in the prediction mode block; and intra-predicting the pixels in each pixel group using the intra prediction mode of each pixel group.

公开(公告)号：US20220191530A1

公开(公告)日：2022-06-16

申请号：US17438263

申请日：2020-03-12

申请人： Hyundai Motor Company ,  Kia Motors Corporation ,  Kwangwoon University Industry-Acadermic Collaboration Foundation

发明人： Dong Gyu Sim ,  Jong Seok Lee ,  Sea Nae Park ,  Jun Taek Park ,  Seung Wook Park ,  Wha Pyeong Lim

IPC分类号： H04N19/46 ,  H04N19/137 ,  H04N19/82 ,  H04N19/159 ,  H04N19/176

摘要： A method and apparatus for intra prediction include a prediction unit that is divided into sub-units and predicted in the sub-units. A video decoding method includes: determining whether to split a current block into multiple subblocks; when the current block is split into the multiple subblocks, determining a split direction for the current block between a horizontal split direction and a vertical split direction and the number of the subblocks, based on split information decoded from a bitstream and a width and a height of the current block; reconstructing the current block by sequentially reconstructing the subblocks, that are specified according to the split direction and the number of the subblocks, using intra prediction; and setting a grid of N samples at regular intervals in horizontal and vertical directions and performing deblock-filtering on, among boundaries between the subblocks in the current block, boundaries that coincide with a boundary of the grid.

公开(公告)号：US10930797B2

公开(公告)日：2021-02-23

申请号：US15374468

申请日：2016-12-09

申请人： HYUNDAI MOTOR COMPANY

发明人： Dae Hwan Chun ,  Youngkyun Jung ,  Nack Yong Joo ,  Junghee Park ,  Jong Seok Lee

IPC分类号： H01L29/872 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/08 ,  H01L29/66

摘要： A Schottky barrier diode includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n− type layer and separated from each other; an anode disposed on the n− type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate. The p type region is in plural, has a hexagonal shape on the plane, and is arranged in a matrix shape, and the n− type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane and encloses the p type region.

公开(公告)号：US09589925B2

公开(公告)日：2017-03-07

申请号：US14800607

申请日：2015-07-15

申请人： HYUNDAI MOTOR COMPANY

发明人： Kyoung-Kook Hong ,  Hyun Woo Noh ,  Youngkyun Jung ,  Dae Hwan Chun ,  Jong Seok Lee ,  Su Bin Kang

IPC分类号： B23K1/00 ,  B23K1/19 ,  H01L23/00 ,  B23K35/02 ,  B23K35/30 ,  B23K20/02

CPC分类号： H01L24/83 ,  B23K1/19 ,  B23K20/02 ,  B23K20/026 ,  B23K35/025 ,  B23K35/3006 ,  B23K2103/08 ,  B23K2103/18 ,  B23K2103/52 ,  B23K2103/56 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/27332 ,  H01L2224/2741 ,  H01L2224/27848 ,  H01L2224/29109 ,  H01L2224/29139 ,  H01L2224/29309 ,  H01L2224/29339 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/32507 ,  H01L2224/83097 ,  H01L2224/832 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/83906

摘要： Disclosed is a method for bonding with a silver paste, the method including: coating a silver paste on a semiconductor device or a substrate, the silver paste containing silver and indium; disposing the semiconductor on the substrate; and heating the silver paste to form a bonding layer, wherein the semiconductor device and the substrate are bonded to each other through the bonding layer, and wherein the indium is contained in the silver paste at 40 mole % or less.

摘要翻译： 公开了一种用银膏粘合的方法，该方法包括：在半导体器件或基板上涂覆银膏，含有银和铟的银膏; 将半导体布置在基板上; 并且加热银膏以形成接合层，其中半导体器件和衬底通过接合层彼此接合，并且其中铟含量在40％（摩尔）以下。

公开(公告)号：US09368649B2

公开(公告)日：2016-06-14

申请号：US14095650

申请日：2013-12-03

申请人： Hyundai Motor Company

发明人： Dae Hwan Chun ,  Jong Seok Lee ,  Kyoung-Kook Hong ,  Youngkyun Jung

IPC分类号： H01L31/075 ,  H01L29/15 ,  H01L29/872 ,  H01L29/66 ,  H01L29/861 ,  H01L29/16

CPC分类号： H01L29/872 ,  H01L29/1608 ,  H01L29/66143 ,  H01L29/8611

摘要： A schottky barrier diode includes an n− type epitaxial layer disposed at a first surface of an n+ type silicon carbide substrate, a plurality of n type pillar areas disposed in the n− type epitaxial layer at a first portion of a first surface of the n+ type silicon carbide substrate, a plurality of p+ areas disposed at a surface of the n− type epitaxial layer and separated from the n type pillar area, a schottky electrode disposed on the n− type epitaxial layer and the p+ area, and an ohmic electrode disposed at a second surface of the n+ type silicon carbide substrate. A doping density of the n type pillar area is larger than a doping density of the n− type epitaxial layer.

摘要翻译： 肖特基势垒二极管包括设置在n +型碳化硅衬底的第一表面上的n型外延层，在n +型碳化硅衬底的第一表面的第一部分处设置在n型外延层中的多个n型衬底区域， 配置在n型外延层的表面并与n型支柱区分离的多个p +区域，设置在n型外延层和p +区域上的肖特基电极以及欧姆电极 设置在n +型碳化硅衬底的第二表面。 n型支柱区域的掺杂密度大于n型外延层的掺杂密度。

公开(公告)号：US09287415B2

公开(公告)日：2016-03-15

申请号：US14468987

申请日：2014-08-26

申请人： Hyundai Motor Company

发明人： Dae Hwan Chun ,  Kyoung-Kook Hong ,  Jong Seok Lee ,  Junghee Park ,  Youngkyun Jung

IPC分类号： H01L51/40 ,  H01L29/872 ,  H01L21/04 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/872 ,  H01L21/046 ,  H01L21/0495 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/6606

摘要： A Schottky barrier diode includes: an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a first p+ region disposed on the n− type epitaxial layer; an n type epitaxial layer disposed on the n− type epitaxial layer and the first p+ region; a second p+ region disposed on the n type epitaxial layer, and being in contact with the first p+ region; a Schottky electrode disposed on the n type epitaxial layer and the second p+ region; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate. Also, the first p+ region has a lattice shape including a plurality of vertical portions and horizontal portions connecting both ends of the respective vertical portions to each other.

摘要翻译： 肖特基势垒二极管包括：n型外延层，设置在n +型碳化硅衬底的第一表面上; 布置在所述n型外延层上的第一p +区; 设置在n型外延层和第一p +区上的n型外延层; 设置在所述n型外延层上并与所述第一p +区接触的第二p +区; 设置在n型外延层和第二p +区上的肖特基电极; 以及设置在n +型碳化硅衬底的第二表面上的欧姆电极。 此外，第一p +区域具有包括将各个垂直部分的两端彼此连接的多个垂直部分和水平部分的格子形状。

公开(公告)号：US09171930B2

公开(公告)日：2015-10-27

申请号：US14143554

申请日：2013-12-30

申请人： Hyundai Motor Company

发明人： Youngkyun Jung ,  Dae Hwan Chun ,  Kyoung-Kook Hong ,  Jong Seok Lee ,  Junghee Park

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66666 ,  H01L21/02104 ,  H01L21/0475 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7813

摘要： A method of manufacturing a semiconductor device may include sequentially forming an n-type epitaxial layer, a p type epitaxial layer, and an n+ region on a first surface of an n+ type silicon carbide substrate; forming a buffer layer on the n+ region; forming a photosensitive film pattern on a part of the buffer layer; etching the buffer layer using the photosensitive film pattern as a mask to form a buffer layer pattern; sequentially forming a first metal layer and a second metal layer which include a first portion and a second portion; removing one or more components to expose a part of the n+ region; and etching the exposed part of the n+ region using the first portion of the first metal layer and the first portion of the second metal layer as masks to form a trench.

摘要翻译： 制造半导体器件的方法可以包括在n +型碳化硅衬底的第一表面上顺序形成n型外延层，p型外延层和n +区; 在n +区上形成缓冲层; 在缓冲层的一部分上形成感光膜图案; 使用感光膜图案作为掩模蚀刻缓冲层以形成缓冲层图案; 顺序地形成包括第一部分和第二部分的第一金属层和第二金属层; 去除一个或多个组件以暴露n +区域的一部分; 以及使用第一金属层的第一部分和第二金属层的第一部分作为掩模蚀刻n +区域的暴露部分以形成沟槽。

公开(公告)号：US09123800B2

公开(公告)日：2015-09-01

申请号：US14317426

申请日：2014-06-27

申请人： Hyundai Motor Company

发明人： Dae Hwan Chun ,  Kyoung-Kook Hong ,  Jong Seok Lee ,  Junghee Park ,  Youngkyun Jung

IPC分类号： H01L29/12 ,  H01L29/16 ,  H01L29/36 ,  H01L29/78 ,  H01L21/205 ,  H01L21/335 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7813

摘要： A semiconductor device includes: a first n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate including a current carrying region and termination regions positioned at both sides of the current carrying region; a p type epitaxial layer disposed on the first n− type epitaxial layer; a second n− type epitaxial layer disposed on the p type epitaxial layer; a first trench disposed in the current carrying region; a second trench disposed in each termination region; a gate insulating layer disposed in the first trench; a gate electrode disposed on the gate insulating layer; and a termination insulating layer disposed in the second trench, in which a side of the termination insulating layer contacts the p type epitaxial layer and the second n− type epitaxial layer.

摘要翻译： 半导体器件包括：第一n型外延层，其设置在n +型碳化硅衬底的第一表面上，该n +型碳化硅衬底包括载流区域和位于载流区域两侧的端接区域; 设置在第一n型外延层上的p型外延层; 设置在p型外延层上的第二n型外延层; 布置在所述载流区域中的第一沟槽; 设置在每个端接区域中的第二沟槽; 设置在所述第一沟槽中的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 以及设置在第二沟槽中的终端绝缘层，其中端接绝缘层的一侧接触p型外延层和第二n-型外延层。