公开(公告)号：US20240395805A1

公开(公告)日：2024-11-28

申请号：US18324559

申请日：2023-05-26

Applicant: Cambridge GaN Devices Limited

Inventor： Florin UDREA ,  Loizos EFTHYMIOU

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01L29/872

Abstract: A III-nitride power semiconductor device comprising a heterojunction transistor, the heterojunction transistor comprising: an active III-nitride semiconductor region comprising at least one heterojunction formed between a GaN layer and a AlGaN layer; a drain terminal operatively connected to the active III-nitride semiconductor region; a source terminal laterally spaced from the drain terminal and operatively connected to the active III-nitride semiconductor region; and a gate terminal positioned over the active III-nitride semiconductor region, the gate terminal being formed between the drain terminal and the source terminal. The power device further comprises a substrate, wherein the substrate comprises a monocrystalline silicon material; a high voltage diode associated with the substrate, the high voltage diode comprising a cathode terminal, an anode terminal and a drift region, wherein at least a part of the drift region is formed within substrate; wherein the heterojunction transistor is positioned over the substrate such that the high voltage diode is located below at least part of the heterojunction transistor, wherein the drift region and is adjacent to and in physical contact with the active III-nitride semiconductor region.

公开(公告)号：US20240395804A1

公开(公告)日：2024-11-28

申请号：US18324319

申请日：2023-05-26

Applicant: Cambridge GaN Devices Limited

Inventor： Florin UDREA ,  Loizos EFTHYMIOU

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01L29/872

Abstract: A power device comprising a substrate, a first wide bandgap semiconductor material positioned over the substrate, wherein the substrate comprises a second wide bandgap semiconductor material different from the first bandgap semiconductor material, a high voltage transistor formed in the first wide bandgap semiconductor material, and a high voltage diode associated with the substrate, wherein at least part of the high voltage diode is positioned below at least part of the high voltage transistor. The high voltage diode comprises a drift region, the drift region formed in the second-wide bandgap material.

公开(公告)号：US12154982B2

公开(公告)日：2024-11-26

申请号：US17496699

申请日：2021-10-07

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Gökhan Atmaca

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/40

Abstract: A transistor device including a layer of AlGaN extending between a source and drain of the device; a GaN channel layer extending under the AlGaN layer; a gate stack including a layer of p-doped gallium nitride; and a layer of p-doped InGaN of at least 5 nm in thickness positioned between the AlGaN layer and the p-doped gallium nitride layer, the InGaN layer having a length greater than a length of the gate stack.

公开(公告)号：US12154964B2

公开(公告)日：2024-11-26

申请号：US17531999

申请日：2021-11-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： An-Hung Tai ,  Yung-Hsiang Chan ,  Shan-Mei Liao ,  Hsin-Han Tsai ,  Jian-Hao Chen ,  Kuo-Feng Yu

IPC: H01L29/51 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes an interface layer on a substrate, a gate dielectric layer on the interface layer, and a work function metal layer on the gate dielectric layer. An interface between the interface layer and the gate dielectric layer has a concentration of a dipole-inducing element. The semiconductor device also includes an oxygen blocking layer on the work function metal layer and a metal fill layer on the oxygen blocking layer.

公开(公告)号：US12154953B2

公开(公告)日：2024-11-26

申请号：US17574652

申请日：2022-01-13

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Ran Li ,  Ching-Lun Ma ,  Leilei Duan ,  Xinru Han

IPC: H01L29/40 ,  H01L21/311 ,  H01L29/423 ,  H10B12/00

Abstract: Disclosed is a method for manufacturing a contact hole, a semiconductor structure and electronic equipment. The method includes: forming a mask layer on an upper end face of a first oxide layer of the semiconductor structure, and exposing a pattern of a target contact hole on the mask layer; exposing a portion, corresponding to a target contact hole, of an upper end face of a contact layer and a portion, corresponding to the target contact hole, of an upper end face of an upper layer structure; depositing a second insulation layer on an etched surface, and depositing a second oxide layer on the second insulation layer; and removing portions, above the upper end face of the first oxide layer, of the second insulation layer and the second oxide layer, and removing a part of the contact layer, and exposing an upper end face of a zeroth layer contact.

公开(公告)号：US12154951B2

公开(公告)日：2024-11-26

申请号：US18178893

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shih-Ya Lin ,  Chung-En Tsai ,  Chee-Wee Liu

IPC: H01L29/161 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

公开(公告)号：US20240387673A1

公开(公告)日：2024-11-21

申请号：US18787177

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng CHANG ,  Chan-Lon YANG ,  Perng-Fei YUH

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

公开(公告)号：US20240387657A1

公开(公告)日：2024-11-21

申请号：US18785186

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Ting Chung ,  Chien-Hong Chen ,  Mahaveer Sathaiya Dhanyakumar ,  Hou-Yu Chen ,  Jin Cai ,  Kuan-Lun Cheng

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/40 ,  H10K10/46 ,  H10K10/84 ,  H10K85/20

Abstract: Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

公开(公告)号：US20240387655A1

公开(公告)日：2024-11-21

申请号：US18787182

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Hong-Ming Wu ,  Chen-Yuan Kao ,  Li-Hsiang Chao ,  Yi-Ying Liu

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/538 ,  H01L29/40

Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

公开(公告)号：US20240387376A1

公开(公告)日：2024-11-21

申请号：US18788189

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yi-Bo LIAO ,  Yu-Xuan HUANG ,  Hou-Yu CHEN ,  Kuan-Lun CHENG

IPC: H01L23/528 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments of the present disclosure provide semiconductor devices having a front side to backside conductive path through a source/drain feature. In some embodiments, the front side to backside conductive path may be formed through a source/drain feature in a standard cell. The other embodiments, the front side to backside conductive path is formed through a source/drain feature in a filler cell. The front side to backside conductive path enables flexible routing for local connections, backside signal connections, and/or backside power rail connection.