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136 条记录 (耗时 0.014 秒)

    Bistable multivibrator circuit
    63.
    发明授权
    Bistable multivibrator circuit 失效
    双向多功能电路

    公开(公告)号：US3912950A

    公开(公告)日：1975-10-14

    申请号：US43929174

    申请日：1974-02-04

    申请人： SONY CORP

    发明人： TADA MASAHIRO

    IPC分类号： H03K3/289 ,  H03K3/286

    CPC分类号： H03K3/289

    摘要： A bistable multivibrator circuit, which is readily adaptable to monolithic integrated circuit technology, combines master and slave portions, thus reducing the components needed to provide a master/slave circuit operation when the multivibrator is used as a frequency divider.

    Master-slave binary divider circuit
    64.
    发明授权
    Master-slave binary divider circuit 失效
    主从分支二极管电路

    公开(公告)号：US3814953A

    公开(公告)日：1974-06-04

    申请号：US31912172

    申请日：1972-12-29

    申请人： IBM

    发明人： MALAVIYA S

    IPC分类号： H03K3/289 ,  H03K3/12 ,  H03K3/286

    CPC分类号： H03K3/289

    摘要： A binary divider circuit of the master-slave type. The master bistable flip-flop and the slave bistable flip-flop are arranged in series between the voltage supply lines so that current flows from one of the supply lines through one of the bistable circuits and then through the other of the bistable circuits into the other supply line. The series arrangement of the bistable circuits provides reduced power dissipation and increased switching speed. The disclosed embodiment further comprises diodes extending from one voltage supply line to the master bistable circuit for bypassing current around the slave bistable circuit and to the master bistable circuit so as to provide higher output power and/or faster switching speed for the master bistable circuit. The diodes further function as a voltage regulator for maintaining the voltage across each bistable circuit approximately constant to prevent the bistable circuits from interacting with each other as their respective impedances vary during switching operations.

    摘要翻译： 主从型二进制分频电路。 主双稳态触发器和从双向触发器串联布置在电压供应线之间，使得电流从一条供电线通过一条双稳态电路然后通过另一条双稳态电路流入另一条 供应线。 双稳态电路的串联布置降低了功耗并提高了开关速度。 所公开的实施例还包括从一个电压供应线延伸到主双稳态电路的二极管，用于绕过从双稳态电路和主双稳态电路旁路电流，以便为主双稳态电路提供更高的输出功率和/或更快的开关速度。 二极管进一步用作电压调节器，用于在每个双稳态电路之间保持大致恒定的电压，以防止双稳态电路在开关操作期间各自的阻抗变化时彼此相互作用。

    Master slave flip-flop
    65.
    发明授权
    Master slave flip-flop 失效
    主从SLIPVE FLIP-FLOP

    公开(公告)号：US3617776A

    公开(公告)日：1971-11-02

    申请号：US3617776D

    申请日：1969-03-13

    申请人： MOTOROLA INC

    发明人： PRIEL URY

    IPC分类号： H03K3/289 ,  H03K19/086 ,  H03K3/12

    CPC分类号： H03K3/289 ,  H03K19/0866

    摘要： Disclosed is a master slave flip-flop including two bistable logic stages, each of which includes transistors which are crossconnected to alternately conduct as binary information is applied to the stages. Both logic stages are connected to receive clock signals which enable binary information to be applied to and stored by one of the two logic stages and thereafter shifted into the other stage when the level of clock signals changes.

    Bistable flip-flop circuit with improved control of clock threshold
    66.
    发明授权
    Bistable flip-flop circuit with improved control of clock threshold 失效
    具有改进的时钟阈值控制的双向FLIP-FLOP电路

    公开(公告)号：US3553497A

    公开(公告)日：1971-01-05

    申请号：US3553497D

    申请日：1968-03-01

    申请人： STEWART WARNER CORP

    发明人： SMITH WILLIAM C

    IPC分类号： H03K3/289 ,  H03K3/12

    CPC分类号： H03K3/289

    摘要： A bistable flip-flop circuit for use preferably in monolithic semiconductor integrated circuits having a master flip-flop at the circuit input and a slave output at the circuit output with coupling transistors between the two master and slave flip-flops. The emitters of the transistors coupled through a resistor to the clock pulse input so that the master flip-flop changes state responsive to the rise time of the clock pulse and the slave flip-flop changes state during the fall time of the clock pulse throughout an extended temperature range.

    Semiconductor integrated circuit
    70.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US09306541B2

    公开(公告)日：2016-04-05

    申请号：US14110330

    申请日：2012-03-21

    申请人： Yasuyuki Suzuki

    发明人： Yasuyuki Suzuki

    IPC分类号： H03K17/16 ,  H03H11/28 ,  H03F3/45 ,  H03F1/38 ,  H03K3/2885 ,  H03K3/289

    CPC分类号： H03H11/28 ,  H03F1/38 ,  H03F3/45085 ,  H03F3/45475 ,  H03F2203/45138 ,  H03F2203/45652 ,  H03K3/2885 ,  H03K3/289

    摘要： In an integrated circuit having a feedback amplifier circuit composed of the feedback which feedbacks a part of the output signal to the input side in the first stage, a semiconductor integrated circuit of the present invention can suppress the occurrence of the data signal distortion and the gain peaking of the frequency characteristic generated by inter-stage wiring between the first stage and the latter stage.A semiconductor integrated circuit of the present invention includes the first circuit and the second circuit having the first output connected to the first circuit, and the second output that is a signal similar to said first output is outputted from between said first circuit and said second circuit. In addition, a semiconductor integrated circuits of the present invention has the feature that the output impedance pulled out from between said first circuit and said second circuit, the input impedance of the circuit connected to the latter stage of said second circuit and the characteristic impedance of the wiring which connects said second output with a circuit connected to the latter stage of said second circuit are equal to each other.

    摘要翻译： 在具有反馈放大电路的集成电路中，反馈放大电路由在第一级反馈输出信号的一部分输入侧的反馈构成，本发明的半导体集成电路可以抑制数据信号失真和增益的发生 在第一阶段和后一阶段之间由阶段布线产生的频率特性的峰值。 本发明的半导体集成电路包括具有连接到第一电路的第一输出的第一电路和第二电路，并且作为类似于所述第一输出的信号的第二输出从所述第一电路和所述第二电路之间输出 。 此外，本发明的半导体集成电路具有从所述第一电路和所述第二电路之间拉出的输出阻抗，连接到所述第二电路的后级的电路的输入阻抗和所述第二电路的特性阻抗 将所述第二输出与连接到所述第二电路的后级的电路连接的布线彼此相等。