发明授权
US3553497A Bistable flip-flop circuit with improved control of clock threshold 失效
具有改进的时钟阈值控制的双向FLIP-FLOP电路

Bistable flip-flop circuit with improved control of clock threshold
摘要:
A bistable flip-flop circuit for use preferably in monolithic semiconductor integrated circuits having a master flip-flop at the circuit input and a slave output at the circuit output with coupling transistors between the two master and slave flip-flops. The emitters of the transistors coupled through a resistor to the clock pulse input so that the master flip-flop changes state responsive to the rise time of the clock pulse and the slave flip-flop changes state during the fall time of the clock pulse throughout an extended temperature range.
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