发明授权
US3553497A Bistable flip-flop circuit with improved control of clock threshold
失效
具有改进的时钟阈值控制的双向FLIP-FLOP电路
- 专利标题: Bistable flip-flop circuit with improved control of clock threshold
- 专利标题(中): 具有改进的时钟阈值控制的双向FLIP-FLOP电路
-
申请号: US3553497D申请日: 1968-03-01
-
公开(公告)号: US3553497A公开(公告)日: 1971-01-05
- 发明人: SMITH WILLIAM C
- 申请人: STEWART WARNER CORP
- 专利权人: Stewart Warner Corp
- 当前专利权人: Stewart Warner Corp
- 优先权: US70967568 1968-03-01
- 主分类号: H03K3/289
- IPC分类号: H03K3/289 ; H03K3/12
摘要:
A bistable flip-flop circuit for use preferably in monolithic semiconductor integrated circuits having a master flip-flop at the circuit input and a slave output at the circuit output with coupling transistors between the two master and slave flip-flops. The emitters of the transistors coupled through a resistor to the clock pulse input so that the master flip-flop changes state responsive to the rise time of the clock pulse and the slave flip-flop changes state during the fall time of the clock pulse throughout an extended temperature range.
信息查询
IPC分类: