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公开(公告)号：US4493095A
公开(公告)日：1985-01-08
申请号：US378356
申请日：1982-05-14
申请人： Akira Yazawa
发明人： Akira Yazawa
摘要： An improved counter wherein consecutively cascaded flip-flops of the prior art are divided into two groups. A first detector produces a first signal in response to a predetermined set of flip-flop states of the first group. A second detector produces a second signal in response to a predetermined set of flip-flop states of the second group. A third detector produces a count output in response to simultaneous existence of the first and second signals. The output from the first group is arranged in phase so that the second signal may be produced before the count output is produced, by applying an inverted output of the first group to the input of the second group.
摘要翻译： 一种改进的计数器，其中先有技术的连续级联的触发器被分成两组。 第一检测器响应于第一组的预定触发器状态集合产生第一信号。 第二检测器响应于第二组的预定触发器状态集合产生第二信号。 第三检测器响应于同时存在第一和第二信号而产生计数输出。 来自第一组的输出被同相布置，使得可以在产生计数输出之前产生第二信号，通过将第一组的反相输出应用于第二组的输入。
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公开(公告)号：US4156819A
公开(公告)日：1979-05-29
申请号：US851753
申请日：1977-11-15
申请人： Toru Takahashi , Kodo Kimura
发明人： Toru Takahashi , Kodo Kimura
CPC分类号： H03K3/289 , H03K3/2865 , H03K3/288
摘要： A logic circuit, which includes master-slave flip-flops, advantageously designed to place both the master and the slave flip-flops in a predetermined logic state so that the logic circuit can be tested in one clock cycle in the same manner as a combinational logic circuit is tested.
摘要翻译： 包括主从触发器的逻辑电路有利地设计成将主触发器和从触发器都放置在预定的逻辑状态，使得逻辑电路可以以与组合的相同的方式在一个时钟周期内进行测试 逻辑电路被测试。
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公开(公告)号：US3786239A
公开(公告)日：1974-01-15
申请号：US3786239D
申请日：1971-05-17
CPC分类号： G05B19/07
摘要： A plurality of memory relays have their respective set coils connected in series with and between channel terminals of a first rough setting matrix and a first fine setting matrix, and have their respective reset coils connected in series with and between channel terminals of a second rough setting matrix and a second fine setting matrix. The timing terminals of the first and second rough setting matrices are connected to the output terminals of a rough counting relay and the timing terminals of the first and second fine setting matrixes are connected to the output terminals of a fine counting relay. These counting relays are supplied with clock pulses for counting operation by means of a clock pulse source. Each memory relay is driven to a set state in response to an output provided at a corresponding channel terminal at a time point preset in the first setting matrixes and is driven to a reset state in response to an output provided at a corresponding channel terminal at a time point preset in the second setting matrixes. Means for controlling the pulse repetition frequency of the clock pulse and for returning said counting relays and memory relays are provided and frequency control and return operation are controlled advantageously by means of said memory relays.
摘要翻译： 多个存储器继电器具有与第一粗设置矩阵和第一精细设置矩阵的通道端之间串联连接的各自的设定线圈，并且其各自的复位线圈与第二粗设置的通道端子串联连接 矩阵和第二精细设置矩阵。 第一和第二粗略设定矩阵的定时端子连接到粗略计数继电器的输出端子，并且第一和第二精细设置矩阵的定时端子连接到精细计数继电器的输出端子。 这些计数继电器提供时钟脉冲，用于通过时钟脉冲源进行计数操作。
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公开(公告)号：US3568071A
公开(公告)日：1971-03-02
申请号：US3568071D
申请日：1968-10-21
申请人： SINGER CO
发明人： KOCHER BEAT A
IPC分类号： G01R29/027 , H04L1/20 , H03K21/32
CPC分类号： H04L1/20 , G01R29/0273
摘要： In a system for accepting each change of signal level as part of a message pulse only if it persists for a prescribed time, that time is measured with a high-speed counter to give high precision and to reduce the jitter that is imposed on the recovered message. A separate counter for each input signal level runs in response to that level and is reset in response to the other level. On reaching a prescribed count it passes a signal to an output flip-flop.
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公开(公告)号：US3562654A
公开(公告)日：1971-02-09
申请号：US3562654D
申请日：1968-05-21
申请人： COLLINS RADIO CO
发明人： CONANT PAUL L SR
CPC分类号： H03K23/66
摘要： AN ELECTRONIC COUNTER INCLUDING A PLURALITY OF SERIALLY CONNECTED FLIP-CLOPS WITH THE FIRST FLIP-FLOP CONNECTED TO RECEIVE A CLOCK INPUT SIGNAL AND THE OUTPUT OF EACH FLIPFLOP PROVIDING THE TRIGGER INPUT TO THE SUCCEEDING FLIP-FLOP. OUTPUTS OF SELECTED FLIP-FLOPS, IN ACCORDANCE WITH A DESIRED COUNT RATIO, ARE CONNECTED TO THE INPUTS OF AN AND GATE, AND THE OUTPUT OF THE AND GATE IS CONNECTED TO THE COUNTER OUTPUT TERMINAL. ALL OTHER FLIP-FLOP OUTPUTS ARE CONNECTED TO THE INPUTS TO AN OR GATE WITH THE OUTPUT OF THE OR GATE OPERATIVELY CONNECTED TO SWITCH MEANS FOR CLAMPING OFF THE COUNTER OUTPUT TERMINAL.
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公开(公告)号：US3550015A
公开(公告)日：1970-12-22
申请号：US3550015D
申请日：1968-03-26
申请人： US NAVY
CPC分类号： H03K23/665 , H03K23/66 , H03L7/191
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7.发明授权Automatic echo-chamber for measuring single time intervals by replication and averaging 失效自动回波室，用于通过复制和平均测量单个时间间隔
公开(公告)号：US4383166A
公开(公告)日：1983-05-10
申请号：US136142
申请日：1980-03-31
申请人： David C. Chu , Robert W. Offermann
发明人： David C. Chu , Robert W. Offermann
IPC分类号： G01R29/027 , H03K21/32 , G07C1/02
CPC分类号： G01R29/0273
摘要： A method is provided for measuring a single-shot time interval using startable oscillators to replicate indefinitely the time interval for averaging. Also provided is a circuit for automatically selecting a proper ratio of division to ensure that the interval being measured is less than the period of replication.
摘要翻译： 提供了一种用于使用可启动振荡器测量单次时间间隔以无限期复制用于平均的时间间隔的方法。 还提供了一种用于自动选择适当的除法比率以确保所测量的间隔小于复制周期的电路。
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公开(公告)号：US4284954A
公开(公告)日：1981-08-18
申请号：US31859
申请日：1979-04-20
CPC分类号： G04G15/006 , H03K17/6285
摘要： A sequential activation control for selective sequential switching of at least two power circuits including: direct current power supply means to provide direct current source of power at selected voltage, clock means to provide output timing pulses at selected intervals, counter means, with counter controller means to receive the clock pulses having multiple electrical output means wherein a portion of the output means are serially activated by the counter controller in response to a selected number of clock pulses until a selected number of output means have been activated to provide a first activation cycle, multiple switch means, at least one switch means for each output means to be operated by selected output means, reset means to deactivate all of the switch means at selected time after the last output means has been activated so the clock means initiates a new activation cycle where the switch means are adapted to activate associated cooperative power circuits.
摘要翻译： 一种用于至少两个电源电路的选择性顺序切换的顺序激活控制，包括：直流电源装置，用于在所选择的电压下提供直流电源，时钟装置，以选定间隔提供输出定时脉冲，计数器装置，与计数器控制器装置 以接收具有多个电输出装置的时钟脉冲，其中输出装置的一部分响应于选定数量的时钟脉冲而被计数器控制器串行激活，直到选定数量的输出装置被激活以提供第一激活周期， 多个开关装置，用于每个输出装置的至少一个开关装置由选择的输出装置操作;复位装置，用于在最后一个输出装置被激活之后的选定时间停用所有开关装置，从而使得时钟装置启动新的激活周期 其中开关装置适于激活相关联的协作电力电路。
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公开(公告)号：US4229726A
公开(公告)日：1980-10-21
申请号：US963462
申请日：1978-11-24
CPC分类号： G08G1/065 , G08G1/012 , G08G1/0129 , G08G1/015
摘要： Apparatus for recording traffic events occurring at a variety of vehicular traffic passageways, such apparatus including a portable housing unit having a keyboard presenting a predetermined pattern of pushbutton switches. A plurality of interchangeable display boards, each having different vehicular traffic patterns and symbolic traffic events displayed thereon, are selectively mounted over the keyboard, and each symbolic traffic even coincides with a particular pushbutton when so mounted. Choice of a suitable display board corresponding to a particular intersection and a desired type of traffic count allows a traffic checker to complete a traffic count by merely pressing a push-button switch corresponding to each observed traffic event and its location. The portable housing includes a data processor which places a switch- and time-identified signal in its memory for each pushbutton depression and may later be plugged into a master computer for abstraction, processing, and tabulated print-out of the recorded data according to the pre-programming of the master computer.
摘要翻译： 用于记录在各种车辆通行通道上发生的交通事件的装置，这种装置包括具有呈现预定图案的按钮开关的键盘的便携式外壳单元。 多个可互换的显示板，其各自具有不同的车辆交通模式和在其上显示的符号交通事件，被选择性地安装在键盘上，并且当这样安装时，每个符号流量甚至与特定的按钮重合。 选择对应于特定交叉点的合适的显示板和期望类型的交通计数允许流量检查器仅通过按压与每个观察到的交通事件及其位置相对应的按钮开关来完成交通量计数。 便携式外壳包括数据处理器，该数据处理器将开关和时间识别的信号放置在其存储器中用于每个按钮按压，并且可以随后插入到主计算机中，用于根据记录数据的抽象，处理和列表打印输出 主计算机的预编程。
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公开(公告)号：US4182961A
公开(公告)日：1980-01-08
申请号：US832463
申请日：1977-09-12
IPC分类号： H03K3/3562 , H03K3/354 , H03K3/356 , H03K21/38 , H03K23/52 , H03K23/54 , H03K23/08 , H03K3/353 , H03K21/32 , H03K21/36
CPC分类号： H03K21/38 , H03K3/356104
摘要： A counter stage having a master section coupled to a slave section in which the transfer of signals between the master and the slave is selectively inhibited. In one embodiment of the invention, an inhibit transmission gate is logically "ANDED" with a clocked transmission gate between the master and slave sections of a counter stage. When the inhibit transmission gate is enabled, the counter stage operates normally. When the inhibit transmission gate is disabled, the states of the master and slave sections cannot change and the count in the stage does not advance. In this and other embodiments, clocking signals are continuously applied to the master-slave sections of a counting stage while transfer of data between the two sections is selectively inhibited. In still other embodiments, the clocking signals to a master-slave counter stage are selectively inhibited to prevent change in the stage.
摘要翻译： 具有耦合到从部分的主部分的计数器级，其中主器件和从器件之间的信号传输被选择性地禁止。 在本发明的一个实施例中，禁止传输门逻辑地与对置级的主部分和从属部分之间的时钟传输门逻辑地“对”。 当禁止传输门被使能时，计数器级正常工作。 当禁止传输门被禁用时，主站和从站的状态不能改变，并且阶段中的计数不会提前。 在该实施例和其他实施例中，时钟信号被连续地施加到计数级的主从部分，同时选择性地禁止两部分之间的数据传输。 在其他实施例中，选择性地禁止到主从计数器级的定时信号以防止级中的变化。
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