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公开(公告)号:US3786239A
公开(公告)日:1974-01-15
申请号:US3786239D
申请日:1971-05-17
CPC分类号: G05B19/07
摘要: A plurality of memory relays have their respective set coils connected in series with and between channel terminals of a first rough setting matrix and a first fine setting matrix, and have their respective reset coils connected in series with and between channel terminals of a second rough setting matrix and a second fine setting matrix. The timing terminals of the first and second rough setting matrices are connected to the output terminals of a rough counting relay and the timing terminals of the first and second fine setting matrixes are connected to the output terminals of a fine counting relay. These counting relays are supplied with clock pulses for counting operation by means of a clock pulse source. Each memory relay is driven to a set state in response to an output provided at a corresponding channel terminal at a time point preset in the first setting matrixes and is driven to a reset state in response to an output provided at a corresponding channel terminal at a time point preset in the second setting matrixes. Means for controlling the pulse repetition frequency of the clock pulse and for returning said counting relays and memory relays are provided and frequency control and return operation are controlled advantageously by means of said memory relays.
摘要翻译: 多个存储器继电器具有与第一粗设置矩阵和第一精细设置矩阵的通道端之间串联连接的各自的设定线圈,并且其各自的复位线圈与第二粗设置的通道端子串联连接 矩阵和第二精细设置矩阵。 第一和第二粗略设定矩阵的定时端子连接到粗略计数继电器的输出端子,并且第一和第二精细设置矩阵的定时端子连接到精细计数继电器的输出端子。 这些计数继电器提供时钟脉冲,用于通过时钟脉冲源进行计数操作。