公开(公告)号：US08633077B2

公开(公告)日：2014-01-21

申请号：US13396872

申请日：2012-02-15

Applicant: Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-Chen Yeh

Inventor： Ming Cai ,  Dechao Guo ,  Liyang Song ,  Chun-Chen Yeh

IPC: H01L21/336

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78684

Abstract: A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses.

Abstract translation: 用于制造具有单轴应力通道的晶体管的方法包括：将绝缘层沉积到衬底上，在绝缘层内限定棒，将沟道凹入衬底中，在沟道中生长第一半导体材料，在栅柱上限定栅叠层， 半导体材料，限定源极和漏极凹部，并将第二半导体材料嵌入到源极和漏极凹部中。

公开(公告)号：US08633071B2

公开(公告)日：2014-01-21

申请号：US13278667

申请日：2011-10-21

Applicant: Duresti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

Inventor： Duresti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

IPC: H01L21/8238

CPC classification number: H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

Abstract translation: 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

公开(公告)号：US20130313655A1

公开(公告)日：2013-11-28

申请号：US13878524

申请日：2012-07-18

Applicant: Guilei Wang ,  Hushan Cui ,  Chao Zhao

Inventor： Guilei Wang ,  Hushan Cui ,  Chao Zhao

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L29/045 ,  H01L29/66553 ,  H01L29/66636

Abstract: A semiconductor device comprises a substrate; a shallow trench isolation embedded in the substrate and forms at least one opening region; a channel region located in the opening region; a gate stack including a gate dielectric layer and a gate electrode layer, located above said channel region; a source/drain region located on both sides of the channel region, including a stress layer which provides strain for the channel region. A liner layer is provided between the shallow trench isolation and the stress layer, which serves as a crystal seed layer of the stress layer. A liner layer and a pad oxide layer are provided between the substrate and the shallow trench isolation. The liner layer is inserted between the STI and the stress layer of the source/drain region as a crystal seed layer or nucleating layer for epitaxial growth, thereby eliminating the STI edge effect during the source/drain strain engineering.

Abstract translation: 半导体器件包括衬底; 嵌入衬底中的浅沟槽隔离物并形成至少一个开口区域; 位于所述开口区域中的通道区域; 包括位于所述沟道区上方的栅极介质层和栅极电极层的栅极堆叠; 位于沟道区两侧的源/漏区，包括为沟道区提供应变的应力层。 衬底层设置在浅沟槽隔离层和应力层之间，其作为应力层的晶种子层。 衬底层和衬垫氧化物层设置在衬底和浅沟槽隔离之间。 衬垫层作为晶种层或用于外延生长的成核层插入到STI和源极/漏极区的应力层之间，从而消除了源极/漏极应变工程中的STI边缘效应。

公开(公告)号：US20130270579A1

公开(公告)日：2013-10-17

申请号：US13913263

申请日：2013-06-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Hua Yu ,  Tze-Liang Lee ,  Pang-Yen Tsai

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7846

Abstract: Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.

Abstract translation: 提供了SOI衬底中具有STI区域的半导体器件的方法和结构。 半导体结构包括在衬底上形成的SOI外延岛。 该结构还包括围绕SOI岛的STI结构。 STI结构包括在衬底上的第二外延层和在第二外延层上的第二电介质层。 一种半导体制造方法包括在衬底上形成介电层并围绕延伸穿过介电层的隔离沟槽围绕衬底中的器件制造区域。 该方法还包括用第一外延层填充隔离沟槽，并在器件制造区域上方和第一外延层上形成第二外延层。 然后用绝缘电介质代替第一外延层的一部分，然后在器件制造区域内形成诸如晶体管的器件的第二外延层。

公开(公告)号：US20130244435A1

公开(公告)日：2013-09-19

申请号：US13889635

申请日：2013-05-08

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Ryo Tanabe

IPC: H01L21/02

CPC classification number: H01L21/02321 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/045 ,  H01L29/7843 ,  H01L29/7846

Abstract: In a second direction, in a plan view, an n-channel MOS transistor and an expanding film are adjacent. Therefore, the n-channel MOS transistor receives a positive stress in the direction in which a channel length is extended from the expanding film. As a result, a positive tensile strain in an electron moving direction is generated in a channel of the n-channel MOS transistor. On the other hand, in the second direction, in a plan view, a p-channel MOS transistor and the expanding film are shifted from each other. Therefore, the p-channel MOS transistor receives a positive stress in the direction in which a channel length is narrowed from the expanding film. As a result, a positive compressive strain in a hole moving direction is generated in a channel of the p-channel MOS transistor. Thus, both on-currents of the n-channel MOS transistor and the p-channel MOS transistor can be improved.

Abstract translation: 在第二方向上，在平面图中，n沟道MOS晶体管和扩展膜相邻。 因此，n沟道MOS晶体管在从扩展膜延伸沟道长度的方向上接收正应力。 结果，在n沟道MOS晶体管的沟道中产生电子移动方向上的正拉伸应变。 另一方面，在第二方向上，在平面图中，p沟道MOS晶体管和扩展膜彼此偏移。 因此，p沟道MOS晶体管在沟道长度从膨胀膜变窄的方向接收正应力。 结果，在p沟道MOS晶体管的沟道中产生空穴移动方向上的正的压缩应变。 因此，可以提高n沟道MOS晶体管和p沟道MOS晶体管的导通电流。

公开(公告)号：US20130240958A1

公开(公告)日：2013-09-19

申请号：US13521051

申请日：2012-05-29

Applicant: Jing Wang ,  Lei Guo ,  Wei Wang

Inventor： Jing Wang ,  Lei Guo ,  Wei Wang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/76283 ,  H01L29/7846

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; an active region formed in the semiconductor substrate, in which the active region comprises: a channel region, and a source region and a drain region formed on both sides of the channel region respectively; and a first isolation trench formed in the semiconductor substrate and on both sides of the active region, in which a first rare earth oxide layer is formed in each first isolation trench to produce a stress in the channel region in a channel length direction.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括：半导体衬底; 形成在所述半导体衬底中的有源区，其中所述有源区包括：沟道区，以及分别形成在所述沟道区两侧的源区和漏区; 以及形成在所述半导体衬底中并且在所述有源区的两侧上形成的第一隔离沟槽，其中在每个第一隔离沟槽中形成第一稀土氧化物层，以在沟道长度方向上的沟道区域中产生应力。

公开(公告)号：US20130181299A1

公开(公告)日：2013-07-18

申请号：US13349942

申请日：2012-01-13

Applicant: Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

Inventor： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.

Abstract translation: 在三维晶体管配置中，至少在漏极和源极区域中提供应变诱导隔离材料，从而引起应变，特别是在三维晶体管的PN结处和附近。 在这种情况下，可以实现卓越的晶体管性能，而在一些说明性实施例中，甚至相同类型的内部应力隔离材料也可能导致P沟道晶体管和N沟道晶体管的优异的晶体管性能。

公开(公告)号：US20130146977A1

公开(公告)日：2013-06-13

申请号：US13816227

申请日：2011-12-01

Applicant: Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L27/12 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/8238 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: The present invention discloses a semiconductor structure comprising: a semiconductor base located on an insulating layer, which is located on a semiconductor substrate; source/drain regions adjacent to opposite first sides of the semiconductor base; gates, positioned on a second set of two sides of the semiconductor base and said second set of two sides are opposite to each other; an insulating plug located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer located between the insulating plug and the semiconductor base wherein the epitaxial layer is SiC for an NMOS device and the epitaxial layer is SiGe for a PMOS device. The present invention further discloses a method for manufacturing a semiconductor structure. The stress at the channel region is adjusted by forming a strained epitaxial layer, thus carrier mobility is improved and the performance of the semiconductor device is improved.

Abstract translation: 本发明公开了一种半导体结构，包括：位于绝缘层上的位于半导体衬底上的半导体基底; 源极/漏极区域与半导体基底的相对的第一侧相邻; 位于所述半导体基底的第二组两侧的所述第二组彼此相对; 位于所述绝缘层上且嵌入所述半导体基底中的绝缘插头; 以及位于绝缘插头和半导体基座之间的外延层，其中外延层是用于NMOS器件的SiC，外延层是用于PMOS器件的SiGe。 本发明还公开了半导体结构的制造方法。 通过形成应变外延层来调整沟道区的应力，从而提高载流子迁移率，提高半导体器件的性能。

公开(公告)号：US08461652B2

公开(公告)日：2013-06-11

申请号：US12568059

申请日：2009-09-28

Applicant: Ryo Tanabe

Inventor： Ryo Tanabe

IPC: H01L21/70

CPC classification number: H01L21/02321 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/045 ,  H01L29/7843 ,  H01L29/7846

Abstract: In a second direction, in a plan view, an n-channel MOS transistor and an expanding film are adjacent. Therefore, the n-channel MOS transistor receives a positive stress in the direction in which a channel length is extended from the expanding film. As a result, a positive tensile strain in an electron moving direction is generated in a channel of the n-channel MOS transistor. On the other hand, in the second direction, in a plan view, a p-channel MOS transistor and the expanding film are shifted from each other. Therefore, the p-channel MOS transistor receives a positive stress in the direction in which a channel length is narrowed from the expanding film. As a result, a positive compressive strain in a hole moving direction is generated in a channel of the p-channel MOS transistor. Thus, both on-currents of the n-channel MOS transistor and the p-channel MOS transistor can be improved.

Abstract translation: 在第二方向上，在平面图中，n沟道MOS晶体管和扩展膜相邻。 因此，n沟道MOS晶体管在从扩展膜延伸沟道长度的方向上接收正应力。 结果，在n沟道MOS晶体管的沟道中产生电子移动方向上的正拉伸应变。 另一方面，在第二方向上，在平面图中，p沟道MOS晶体管和扩展膜彼此偏移。 因此，p沟道MOS晶体管在沟道长度从膨胀膜变窄的方向接收正应力。 结果，在p沟道MOS晶体管的沟道中产生空穴移动方向上的正的压缩应变。 因此，可以提高n沟道MOS晶体管和p沟道MOS晶体管的导通电流。

公开(公告)号：US20130082350A1

公开(公告)日：2013-04-04

申请号：US13686343

申请日：2012-11-27

Applicant: Infineon Technologies AG

Inventor： Armin Tilke ,  Jiang Yan ,  Matthias Hierlemann

IPC: H01L29/04 ,  H01L21/265 ,  H01L23/525 ,  H01L21/76

CPC classification number: H01L29/045 ,  H01L21/76251 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a portion of the insulating layer, and the strained silicon layer is disposed on another portion of the insulating layer and has a crystal orientation different from the first crystal orientation.

Abstract translation: 公开了具有多个晶体取向的绝缘体上硅器件。 在一个实施例中，绝缘体上硅器件包括衬底层，设置在衬底层上的绝缘层，第一硅层和应变硅层。 第一硅层具有第一晶体取向并且设置在绝缘层的一部分上，并且应变硅层设置在绝缘层的另一部分上并且具有不同于第一晶体取向的晶体取向。