公开(公告)号：US09543309B2

公开(公告)日：2017-01-10

申请号：US14823783

申请日：2015-08-11

Applicant: SK hynix Inc.

Inventor： Sung Kun Park

IPC: H01L29/04 ,  H01L29/66 ,  H01L21/02 ,  H01L27/112

CPC classification number: H01L27/11206 ,  H01L23/5252 ,  H01L29/16 ,  H01L29/861

Abstract: An antifuse memory cell includes an antifuse element and a gate PN diode. The antifuse element includes a gate terminal coupled to a word line, a drain terminal coupled to a bit line, and a body terminal. The gate PN diode is coupled between the word line and the gate terminal.

Abstract translation: 反熔丝存储单元包括反熔丝元件和栅极PN二极管。 反熔丝元件包括耦合到字线的栅极端子，耦合到位线的漏极端子和主体端子。 栅极PN二极管耦合在字线和栅极端子之间。

公开(公告)号：US20160379688A1

公开(公告)日：2016-12-29

申请号：US15257359

申请日：2016-09-06

Applicant: eMemory Technology Inc.

Inventor： Wei-Ren Chen ,  Wen-Hao Lee

IPC: G11C5/06 ,  H01L27/115 ,  H01L23/525 ,  H01L27/112 ,  G11C16/04 ,  G11C17/16

CPC classification number: G11C5/06 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/11206 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/93 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array structure of a single-poly nonvolatile memory includes a first MTP section, a first OTP section and a ROM section. The first MTP section includes a plurality of MTP cells, the first OTP section includes a plurality of OTP cells and the first ROM section includes a plurality of ROM cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section. The first ROM section is connected to a third word line, a third source line and the plurality of bit lines shared with the first MTP section.

Abstract translation: 单一多边形非易失性存储器的阵列结构包括第一MTP部分，第一OTP部分和ROM部分。 第一MTP部分包括多个MTP单元，第一OTP部分包括多个OTP单元，并且第一ROM部分包括多个ROM单元。 第一MTP连接到第一字线，第一源极线，第一擦除线和多个位线。 第一OTP部分连接到第二字线，第二源线和与第一MTP部分共享的多个位线。 第一ROM部分连接到第三字线，第三源线和与第一MTP部分共享的多个位线。

公开(公告)号：US09502424B2

公开(公告)日：2016-11-22

申请号：US13684107

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  John Jianhong Zhu ,  Xia Li

IPC: H01L27/112 ,  H01L21/8239 ,  G11C17/16 ,  H01L23/522 ,  H01L23/525 ,  H01L49/02 ,  H01L27/105

CPC classification number: H01L27/11206 ,  G11C17/16 ,  G11C17/165 ,  H01L21/8239 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/1052 ,  H01L27/11286 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region, and the antifuse has a conductor-insulator-conductor structure. The antifuse includes a first conductor that acts as a first electrode, and also includes an antifuse dielectric, and a second conductor. A first surface of the first electrode is coupled to a first surface of the antifuse dielectric, a second surface of the antifuse dielectric is coupled to a first surface of the second conductor. The second conductor is electrically coupled to the access transistor's source/drain region. The antifuse is adapted to transition from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to an antifuse dielectric breakdown voltage is applied between the first electrode and the second conductor.

Abstract translation: 一个特征涉及一种集成电路，包括存取晶体管和反熔丝。 存取晶体管包括至少一个源极/漏极区域，反熔丝具有导体 - 绝缘体 - 导体结构。 反熔丝包括用作第一电极的第一导体，并且还包括反熔丝电介质和第二导体。 第一电极的第一表面耦合到反熔丝电介质的第一表面，反熔丝电介质的第二表面耦合到第二导体的第一表面。 第二导体电耦合到存取晶体管的源/漏区。 如果在第一电极和第二导体之间施加大于或等于抗熔丝电介质击穿电压的编程电压Vpp，则反熔丝适于从开路状态转换到闭合电路状态。

公开(公告)号：US20160336332A1

公开(公告)日：2016-11-17

申请号：US15110706

申请日：2014-02-11

Applicant: Chen-Guan LEE ,  Walid HAFEZ ,  Chia-Hong JAN

Inventor： Chen Guan LEE ,  Walid M. HAFEZ ,  Chia Hong JAN

IPC: H01L27/112 ,  H01L23/525

CPC classification number: H01L27/11206 ,  H01L23/5252 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antifuse may include a non-planar conductive terminal having a high-z portion extending to a greater z-height than a low-z portion. A second conductive terminal is disposed over the low-z portion and separated from the first terminal by at least one intervening dielectric material. Fabrication of an antifuse may include forming a first opening in a first dielectric material disposed over a substrate, and undercutting a region of the first dielectric material. The undercut region of the first dielectric material is lined with a second dielectric material, such as gate dielectric material, through the first opening. A conductive first terminal material backfills the lined undercut region through the first opening. A second opening through the first dielectric material exposes the second dielectric material lining the undercut region. A conductive second terminal material is backfilled in the second opening.

Abstract translation: 反熔丝可以包括具有延伸到比低z部分更大的z高度的高z部分的非平面导电端子。 第二导电端子设置在低z部分之上并且与第一端子分开由至少一个中间介电材料。 反熔丝的制造可以包括在布置在基板上的第一介电材料中形成第一开口，以及对第一介电材料的区域进行底切。 第一介电材料的底切区域通过第一开口衬有诸如栅极电介质材料的第二介电材料。 导电的第一端子材料通过第一开口填充衬里的底切区域。 穿过第一介电材料的第二开口暴露在底切区域内的第二电介质材料。 导电的第二端子材料在第二开口中被回填。

公开(公告)号：US20160300622A1

公开(公告)日：2016-10-13

申请号：US15096170

申请日：2016-04-11

Applicant: NEO Semiconductor, Inc.

Inventor： Fu-Chang Hsu

IPC: G11C17/16 ,  H01L29/06 ,  H01L27/12 ,  G11C17/18 ,  H01L27/088 ,  H01L23/525 ,  H01L27/112

CPC classification number: G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/0886 ,  H01L27/11206 ,  H01L27/1211

Abstract: A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a drain P+ diffusion deposited in the N− well, a source P+ diffusion deposited in the N− well, and an oxide layer deposited on the N− well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.

Abstract translation: 公开了一种CMOS反熔丝单元。 一方面，一种装置包括形成在N阱上的N阱和反熔丝单元。 反熔丝单元包括沉积在N阱中的漏极P +扩散层，沉积在N阱中的源极P +扩散层，以及沉积在N-阱上并且具有与漏极P +扩散重叠的重叠区域的氧化物层。 控制栅极沉积在氧化物层上。 当控制栅极和漏极P +扩散之间的电压差超过氧化物层的电压阈值并形成从控制栅极到漏极P +扩散的泄漏路径时，抗熔丝单元的数据位被编程。 泄漏路径被限制在重叠区域中。

公开(公告)号：US09460859B2

公开(公告)日：2016-10-04

申请号：US13795677

申请日：2013-03-12

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Toshiyuki Nakaiso ,  Yutaka Takeshima ,  Yutaka Ishiura ,  Yuji Irie ,  Shinsuke Tani ,  Jun Takagi

IPC: H01G4/30 ,  H01G4/33 ,  H01L23/522 ,  H01L23/525 ,  H01L27/01

CPC classification number: H01G4/33 ,  H01L23/5223 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53261 ,  H01L27/016 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dielectric thin film element having a high humidity resistance is provided. A dielectric thin film element includes a capacitance section having a dielectric layer and a pair of electrode layers formed on the respective upper and lower surfaces of the dielectric layer 22. Furthermore, a protection layer is provided on the capacitance section, a pair of interconnect layers are drawn out to an upper surface of the protection layer, and external electrodes are formed to be electrically connected to the interconnect layers. Further, first surface metal layers cover a portion of the interconnect layers that extends along the inner surface of the openings and second surface metal layers are formed at end of the first surface metal layers.

Abstract translation: 提供了具有高耐湿性的电介质薄膜元件。 电介质薄膜元件包括具有电介质层的电容部分和形成在电介质层22的相应上表面和下表面上的一对电极层。此外，保护层设置在电容部分上，一对互连层 被拉出到保护层的上表面，并且外部电极形成为与互连层电连接。 此外，第一表面金属层覆盖沿着开口的内表面延伸的互连层的一部分，并且第二表面金属层形成在第一表面金属层的端部。

公开(公告)号：US20160254032A1

公开(公告)日：2016-09-01

申请号：US15151013

申请日：2016-05-10

Applicant: eMemory Technology Inc.

Inventor： Wei-Ren Chen ,  Wen-Hao Lee

IPC: G11C5/06 ,  G11C17/16 ,  G11C16/04

CPC classification number: G11C5/06 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L23/528 ,  H01L27/11206 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/93 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.

公开(公告)号：US09431497B2

公开(公告)日：2016-08-30

申请号：US13899150

申请日：2013-05-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Shyue Seng Tan ,  Elgin Quek

IPC: H01L29/76 ,  H01L29/423 ,  H01L27/112 ,  G11C17/16 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L21/822 ,  H01L23/525

CPC classification number: H01L29/42364 ,  G11C17/16 ,  H01L21/8221 ,  H01L23/5252 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/11206 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/42388 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer.

Abstract translation: 提供具有反熔丝配置的晶体管器件和形成晶体管器件的方法。 示例性晶体管器件包括包括第一鳍片的半导体衬底。 第一绝缘体层覆盖半导体衬底并且具有小于第一鳍片的高度的厚度。 第一鳍延伸穿过第一绝缘体层并突出超过第一绝缘体层以提供掩埋鳍部分和暴露的鳍部分。 栅电极结构覆盖在暴露的鳍部上。 栅绝缘结构设置在第一鳍和栅电极结构之间。 栅极绝缘结构包括覆盖第一鳍片的第一表面的第一介电层。 栅极绝缘结构还包括覆盖第一鳍片的第二表面的第二介电层。 通过第一介电层在第一鳍片和栅极电极结构之间限定电势击穿路径。

公开(公告)号：US09431254B2

公开(公告)日：2016-08-30

申请号：US14681852

申请日：2015-04-08

Applicant: Kilopass Technology, Inc.

Inventor： Harry Shengwen Luan

IPC: H01L21/8239 ,  H01L27/112 ,  H01L21/28 ,  G11C17/16 ,  H01L23/525 ,  H01L29/66

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L21/28008 ,  H01L23/5252 ,  H01L29/66477 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A one time programmable nonvolatile memory formed from metal-insulator semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting lines formed in a semiconductor substrate. Among others, features include forming the gate lines with polysilicon layers of one conductivity type and the intersecting lines with dopants of the opposite conductivity type in the substrate; forming the intersecting lines with differing dopant concentrations near the substrate surface and deeper in the substrate; and forming the widths of the gate lines and intersecting lines with the minimum feature size that can be patterned by a particular semiconductor technology.

Abstract translation: 由金属 - 绝缘体半导体单元形成的一次可编程非易失性存储器。 电池处于形成在半导体衬底中的导电栅极线和相交线的交叉点。 其中，特征包括在衬底中形成具有一种导电类型的多晶硅层的栅极线和与衬底中具有相反导电类型的掺杂剂的相交线; 在衬底表面附近形成具有不同掺杂剂浓度的相交线并且在衬底中形成更深的相交线; 以及通过特定的半导体技术可以图案化的最小特征尺寸形成栅极线和相交线的宽度。

公开(公告)号：US20160233222A1

公开(公告)日：2016-08-11

申请号：US15131982

申请日：2016-04-18

Applicant: SK hynix Inc.

Inventor： Eun Sung LEE

IPC: H01L27/112 ,  G11C17/16 ,  H01L21/768 ,  H01L23/525 ,  H01L27/108

CPC classification number: H01L27/11206 ,  G11C17/16 ,  G11C29/785 ,  G11C29/787 ,  H01L21/76897 ,  H01L23/525 ,  H01L23/5252 ,  H01L27/10844 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse based on a Field Nitride Trap (FNT) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar including a second junction, a selection line buried between the first active pillar and the second active pillar, and a trap layer for electrically coupling the first junction to the second junction by trapping minority carriers according to individual voltages applied to the first junction, the second junction and the selection line. As a result, the fuse can be highly integrated through the above-mentioned structure, and programming of the fuse can be easily achieved.