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    VIRTUAL ENVIRONMENT FOR IMPLEMENTING INTEGRATED PHOTONICS ASSEMBLIES
    66.
    发明公开
    VIRTUAL ENVIRONMENT FOR IMPLEMENTING INTEGRATED PHOTONICS ASSEMBLIES 审中-公开

    公开(公告)号：US20230186005A1

    公开(公告)日：2023-06-15

    申请号：US17922321

    申请日：2021-04-29

    Applicant: SiPhox Inc

    Inventor： Diedrik Rene Vermeulen ,  Michael Dubrovsky

    IPC: G06F30/3308 ,  G06F30/31

    CPC classification number: G06F30/3308 ,  G06F30/31 ,  G06F2111/20

    Abstract: Systems and methods for generating a virtual environment for implementing an integrated photonics assembly are presented. An example system can include one or more processors and a memory coupled with the processors, where the processor executes a plurality of modules stored in the memory. The plurality of modules can include a user interface module for deploying one or more virtual photonic integrated subcircuits within the virtual environment, in which the virtual environment is configured to enable coupling of at least two virtual photonic integrated subcircuits. The coupling of the virtual photonic integrated subcircuits can form a virtual integrated photonics assembly. The modules can include a library module comprising a plurality of virtual photonic integrated subcircuits. One or more virtual photonic integrated subcircuits can include a performance characteristic. The performance characteristic can represent a real-world performance characteristic of a pre-fabricated physical photonic integrated subcircuit corresponding to the virtual photonic integrated subcircuit.

    CORRECT-BY-CONSTRUCTION FILLER CELL INSERTION
    67.
    发明公开
    CORRECT-BY-CONSTRUCTION FILLER CELL INSERTION 审中-公开

    公开(公告)号：US20230169256A1

    公开(公告)日：2023-06-01

    申请号：US17997271

    申请日：2020-04-30

    Applicant: Siemens Industry Software Inc.

    Inventor： Fady Fouad

    IPC: G06F30/398 ,  G06F30/392

    CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2111/20

    Abstract: This application discloses a computing system implementing a yield enhancer tool to extract characteristics of cells from a physical layout design for an integrated circuit, determine locations of vacant regions in the physical layout design, apply electrical design rules for manufacture of the integrated circuit to the extracted characteristics in order to identify cells in the physical layout design that would violate the electrical design rules. The computing system can select filler cells for the vacant regions based, at least in part, on extracted characteristics of the cells abutting the vacant regions and the electrical design rules, and insert the selected filler cells in the vacant regions of the physical design layout. The computing system can perform a design rule check operation, which applies the electrical design rules to the physical design layout having been inserted with the selected filler cells.

    Method and system for identifying conflicts in a roof truss to wall vertical interface
    68.
    发明授权
    Method and system for identifying conflicts in a roof truss to wall vertical interface 有权

    公开(公告)号：US11657192B2

    公开(公告)日：2023-05-23

    申请号：US16802629

    申请日：2020-02-27

    Applicant: Consulting Engineers, Corp.

    Inventor： Maharaj Jalla

    IPC: G06F30/13 ,  E04C3/02 ,  G06F30/12 ,  G06F111/04 ,  G06F111/20

    CPC classification number: G06F30/13 ,  E04C3/02 ,  G06F30/12 ,  G06F2111/04 ,  G06F2111/20

    Abstract: The present invention is a method for accessing a model of a building, selecting a set of roof trusses, wherein the roof trusses comprised of a first set of members, isolating plurality of wall panels, wherein the wall panels are comprised of a second set of members, selecting a group of interfacing members between a roof truss and a wall panel, detecting an interface type between the roof truss and the wall panel, wherein each interface has a predetermined set of requirements, calculating a set of actual values associated with the interface type, comparing the set of actual values with a set of required values and determining the delta of the actual values and the required values, and identifying each interface where the delta is outside a predetermined range.

    EDA pad package library updating/application method and system, medium and terminal
    70.
    发明授权
    EDA pad package library updating/application method and system, medium and terminal 有权

    公开(公告)号：US12111811B2

    公开(公告)日：2024-10-08

    申请号：US17262447

    申请日：2018-09-28

    Applicant: VAYO (SHANGHAI) TECHNOLOGY CO., LTD.

    Inventor： Shengjie Qian ,  Fengshou Liu

    IPC: G06F15/16 ,  G06F16/23 ,  G06F16/953 ,  G06F30/31 ,  G06F30/394 ,  G06F111/20

    CPC classification number: G06F16/23 ,  G06F16/953 ,  G06F30/31 ,  G06F30/394 ,  G06F2111/20

    Abstract: An EDA pad package library updating/application method and system, a medium, and a terminal. The method includes: extracting a graphic data of a pad and setting information of a component based on the pad from an EDA wiring data; querying and downloading a graphic model of the component according to attribute information of the component; forming a simulated package pad by simulating and assembling the graphical model of the component and the graphical data of the pad according to setting information of the component based on the pad; storing the simulated package pad in a model database, updating an existed EDA pad package library by associating the simulated package pad to a predetermined keyword/words in the model database. A package pad created by others can be quickly obtained without a package pad library. The best pads that have been verified can be updated continuously and quickly.

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