公开(公告)号：US11793091B2

公开(公告)日：2023-10-17

申请号：US17114438

申请日：2020-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Da-Jun Lin ,  Chih-Wei Chang ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L45/00 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10N70/063 ,  H10B63/00 ,  H10N70/028 ,  H10N70/041 ,  H10N70/841 ,  H10N70/8833

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.

公开(公告)号：US20230329004A1

公开(公告)日：2023-10-12

申请号：US18209482

申请日：2023-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US11723287B2

公开(公告)日：2023-08-08

申请号：US17956772

申请日：2022-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Shih-Wei Su ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.

公开(公告)号：US11707003B2

公开(公告)日：2023-07-18

申请号：US17140981

申请日：2021-01-04

Applicant: United Microelectronics Corp.

Inventor： Chich-Neng Chang ,  Da-Jun Lin ,  Shih-Wei Su ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/24 ,  H10B63/30 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

公开(公告)号：US11676920B2

公开(公告)日：2023-06-13

申请号：US17159080

申请日：2021-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L2224/05124 ,  H01L2224/45147 ,  H01L2224/45464

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

公开(公告)号：US11521895B2

公开(公告)日：2022-12-06

申请号：US17325125

申请日：2021-05-19

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chich-Neng Chang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. The air gap has a cross-section of substantially bottle shape with a flat top. A porous dielectric layer is disposed over the substrate, sealing the flat top of the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

公开(公告)号：US20220246839A1

公开(公告)日：2022-08-04

申请号：US17725511

申请日：2022-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

公开(公告)号：US20220140229A1

公开(公告)日：2022-05-05

申请号：US17573641

申请日：2022-01-12

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10

Abstract: A method for fabricating memory cell of magnetoresistive RAM includes forming a memory stack structure on a first electrode layer. The memory stack structure includes a SAF layer to serve as a pinned layer; a magnetic free layer and a barrier layer sandwiched between the SAF layer and the magnetic free layer. A second electrode layer is then formed on the memory stack structure. The SAF layer includes a first magnetic layer, a second magnetic layer, and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first and second magnetic layers, and the second metal element of the first magnetic layer and the second magnetic layer interfaces with the spacer layer.

公开(公告)号：US20220140002A1

公开(公告)日：2022-05-05

申请号：US17106214

申请日：2020-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US11258005B2

公开(公告)日：2022-02-22

申请号：US16656304

申请日：2019-10-17

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/10

Abstract: A cell structure of magnetoresistive RAM includes a synthetic anti-ferromagnetic (SAF) layer to serve as a pinned layer; a barrier layer, disposed on the SAF layer; and a magnetic free layer, disposed on the barrier layer. The SAF layer includes: a first magnetic layer; a second magnetic layer; and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first magnetic layer and the second magnetic layer interfacing with the spacer layer.