公开(公告)号：US09761658B2

公开(公告)日：2017-09-12

申请号：US14718841

申请日：2015-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cong-Min Fang ,  Kang-Min Kuo ,  Shi-Min Wu

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L29/0657

Abstract: A semiconductor structure includes a semiconductor substrate, a first active area, a second active area, a first trench, at least one raised portion, and a first dielectric. The first active area is in the semiconductor substrate. The second active area is in the semiconductor substrate. The first trench is in the semiconductor substrate and separates the first active area and the second active area from each other. The raised portion is raised from the semiconductor substrate and is disposed in the first trench. The first dielectric is in the first trench and covers the raised portion.

公开(公告)号：US20170162573A1

公开(公告)日：2017-06-08

申请号：US14961900

申请日：2015-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Chi Tsai ,  Kang-Min Kuo

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/266 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/265 ,  H01L21/266 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/66545 ,  H01L29/7843

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, and a dielectric layer. The MOS transistor includes a gate structure formed over the substrate. The dielectric layer is formed aside the gate structure, and the dielectric layer is doped with a strain modulator. A lattice constant of the strain modulator is larger than a lattice constant of an atom of the dielectric layer.

公开(公告)号：US09412866B2

公开(公告)日：2016-08-09

申请号：US13924731

申请日：2013-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gwo-Chyuan Kuoh ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien ,  Yen-Ming Peng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L29/7843 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/823871 ,  H01L23/00 ,  H01L29/7842 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.

Abstract translation: 本公开内容涉及具有一个或多个后端行（BEOL）选择应力膜的集成芯片，其应用提高BEOL选择应力膜的半导体器件的性能的应力，以及相关的方法 形成。 在一些实施例中，集成芯片具有带有一个或多个具有第一器件类型的半导体器件的半导体衬底。 应力传递元件位于一个或多个半导体器件上方的位置处的后端行堆叠中。 选择应力膜位于应力转移元件上方。 选择应力膜在应力转移元件上引起应力，其中应力具有取决于一个或多个半导体器件的第一器件类型的压缩或拉伸状态。 应力作用在一个或多个半导体器件上以提高它们的性能。

公开(公告)号：US20150294914A1

公开(公告)日：2015-10-15

申请号：US14248755

申请日：2014-04-09

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L27/088 ,  H01L21/321 ,  H01L21/311 ,  H01L21/02 ,  H01L21/285 ,  H01L21/28 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0607 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621

Abstract: A semiconductor device with an increased effective gate length or an increased effective channel width, and a method of forming the same are provided. The effective gate length or the effective channel width of the device is increased by lowering a top surface of an oxide isolation structure below the gate of the semiconductor device.

Abstract translation: 提供了具有增加的有效栅极长度或增加的有效沟道宽度的半导体器件及其形成方法。 通过将半导体器件的栅极下方的氧化物隔离结构的顶表面降低来增加器件的有效栅极长度或有效沟道宽度。

公开(公告)号：US09093528B2

公开(公告)日：2015-07-28

申请号：US13905438

申请日：2013-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ming Peng ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/498 ,  H01L21/8234

CPC classification number: H01L29/7843 ,  H01L21/82345 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices.

Abstract translation: 本公开涉及具有一个或多个后端（BEOL）应力补偿层的集成芯片，其减小一个或多个下层半导体器件上的应力，以及相关联的形成方法。 在一些实施例中，集成芯片具有带有一个或多个半导体器件的半导体衬底。 应力元件位于覆盖一个或多个半导体器件的位置处的后端行堆叠中。 应力层位于应力元件上方会对应力元件产生应力。 位于应力元件上方的应力补偿层提供反应力，以减轻应力层对受应力元件的应力。 通过减少在应力元件上产生的应力，减小半导体衬底上的应力，提高一个或多个半导体器件的性能的均匀性。

公开(公告)号：US09093373B2

公开(公告)日：2015-07-28

申请号：US13965294

申请日：2013-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chia Chang ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L27/146 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L21/265 ,  H01L21/26513 ,  H01L21/76286 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/1463 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit includes a p-type region formed beneath a surface of a semiconductor substrate, and an n-type region formed beneath the surface of the semiconductor substrate. The n-type region meets the p-type region at a p-n junction. A diffusion barrier structure, which is beneath the surface of the semiconductor substrate and extends along a side of the p-n junction, limits lateral diffusion between the p-type region and n-type region.

Abstract translation: 集成电路包括形成在半导体衬底的表面下方的p型区域和形成在半导体衬底的表面下方的n型区域。 n型区域在p-n结处与p型区域相遇。 在半导体衬底的表面下方并且沿着p-n结的一侧延伸的扩散阻挡结构限制了p型区域和n型区域之间的横向扩散。