公开(公告)号：US20180366375A1

公开(公告)日：2018-12-20

申请号：US15628345

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Tzu-Chiang Chen ,  Chih-Sheng Chang ,  Cheng-Hsien Wu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.

公开(公告)号：US10147819B2

公开(公告)日：2018-12-04

申请号：US15464484

申请日：2017-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Chih Chieh Yeh ,  Cheng-Hsien Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

公开(公告)号：US11699620B2

公开(公告)日：2023-07-11

申请号：US17225249

申请日：2021-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Yi-Jing Li ,  Chen-Heng Li

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

公开(公告)号：US11515305B2

公开(公告)日：2022-11-29

申请号：US16688047

申请日：2019-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/324 ,  H01L29/161

Abstract: A structure and a formation method of hybrid semiconductor devices are provided. The structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The structure further includes a gate stack over the nanostructures. The nanostructures are separated from each other by portions of the gate stack.

公开(公告)号：US11437468B2

公开(公告)日：2022-09-06

申请号：US17120852

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.

公开(公告)号：US11239367B2

公开(公告)日：2022-02-01

申请号：US16914831

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Chih Chieh Yeh ,  Cheng-Hsien Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

公开(公告)号：US11195763B2

公开(公告)日：2021-12-07

申请号：US16556096

申请日：2019-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  Ta-Pen Guo ,  Yu-Lin Yang ,  I-Sheng Chen ,  Szu-Wei Huang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

公开(公告)号：US11158542B2

公开(公告)日：2021-10-26

申请号：US16676871

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Tung-Ying Lee ,  Szu-Wei Huang ,  Huan-Sheng Wei

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a number of first semiconductor wires over a semiconductor substrate, and the first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure includes a first gate stack partially wrapping the first semiconductor wires, and a spacer element adjacent to the first gate stack. Each of the first semiconductor wires has a first portion directly below the spacer element and a second portion directly below the first gate stack, the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.

公开(公告)号：US11107931B2

公开(公告)日：2021-08-31

申请号：US16574318

申请日：2019-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wilman Tsai ,  Cheng-Hsien Wu ,  I-Sheng Chen ,  Stefan Rusu

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L27/088 ,  H01L21/8234

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate including a first fin portion, a first nanostructure over the first fin portion. The first nanostructure has a dumbbell shape. The first nanostructure includes a semiconductor material layer over the first fin portion, and a cladding layer surrounding the semiconductor material layer. The semiconductor material layer has a rectangular shape, and the cladding layer has a hexagonal or quadrilateral shape. The semiconductor device structure includes a first gate structure surrounding the first nanostructure.

公开(公告)号：US10998429B2

公开(公告)日：2021-05-04

申请号：US16585278

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L21/308 ,  H01L21/265 ,  H01L29/10

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.