公开(公告)号：US20240363690A1

公开(公告)日：2024-10-31

申请号：US18306421

申请日：2023-04-25

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Ming-Huei Lin ,  Junjing Bao

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Gate-all-around (GAA) field-effect transistor (FET) device employing strain material structure in inactive gate region(s) of a gate for applying channel strain to the channel(s) of the GAA FET for increased carrier mobility. The GAA FET device includes a GAA P-type (P) FET (PFET) and a GAA N-type (N) FET (NFET) served by a gate with a strain material in the inactive gate region(s) of the gate adjacent to the active gates of the GAA NFET and GAA PFET. In this manner, the strain material applies strain to both the GAA NFET and GAA PFET channels in the elongated direction of the gate in a direction orthogonal to their channel directions between the respective sources and drains, so that a strain material of the same strain type can be used to increase carrier mobility of both the GAA NFET and GAA PFET alike.

公开(公告)号：US12068238B2

公开(公告)日：2024-08-20

申请号：US17234166

申请日：2021-04-19

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Junjing Bao ,  Haining Yang

IPC: H01L23/522 ,  H01L23/552 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5228 ,  H01L23/552 ,  H01L28/87

Abstract: A metal oxide metal (MOM) capacitor and methods for fabricating the same are disclosed. The MOM capacitor includes a first metal layer having a first plurality of fingers, each of the first plurality of fingers configured to have alternating polarities. A high resistance (Hi-R) conductor layer is disposed adjacent the first metal layer in a plane parallel to the first metal layer.

公开(公告)号：US11901434B2

公开(公告)日：2024-02-13

申请号：US17245695

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Haining Yang ,  Youseok Suh

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L29/417

CPC classification number: H01L29/66515 ,  H01L21/0217 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/41775

Abstract: In some aspects, a semiconductor die includes an insulation layer disposed on a substrate, a gate spacer disposed in the insulation layer, a gate disposed between the gate spacer, a first dielectric gate layer disposed on the gate between the gate spacer, a second dielectric gate layer disposed on the first dielectric gate layer between the gate spacer, a gate contact coupled to the gate and in contact with the first dielectric gate layer and the second dielectric gate layer, and a source/drain contact that has a single inner spacer.

公开(公告)号：US11545483B2

公开(公告)日：2023-01-03

申请号：US16712222

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Haining Yang ,  Bin Yang

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/78

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

公开(公告)号：US11056487B2

公开(公告)日：2021-07-06

申请号：US16569911

申请日：2019-09-13

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang

IPC: H01L27/088 ,  H01L21/762 ,  H01L23/535

Abstract: Certain aspects of the present disclosure generally relate to a single diffusion break having a conductive portion. An example semiconductor device generally includes a first semiconductor region, a second semiconductor region, a dielectric region, and a single diffusion break (SDB). The dielectric region is disposed between the first semiconductor region and the second semiconductor region. The SDB intersects at least one of the first semiconductor region or the second semiconductor region, and the SDB comprises an electrically conductive portion.

公开(公告)号：US11011602B2

公开(公告)日：2021-05-18

申请号：US16196388

申请日：2018-11-20

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang

IPC: H01L29/06 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/764

Abstract: Circuits employing an adjacent low-k dummy gate to a field-effect transistor (FET) to reduce FET source/drain parasitic capacitance, and related fabrication methods. To reduce or mitigate an increase in the source/drain parasitic capacitance(s) of a FET, a dummy gate adjacent to an active gate of the FET is provided to have a low-k (i.e., low relative permittivity). In this manner, the relative permittivity (k) between the source/drain of the FET and an adjacent dummy gate and/or source/drain of another FET is reduced, thereby reducing the parallel plate capacitance of the FET(s). Reducing parasitic capacitance of the FET(s) may allow further reduced scaling of the circuit to offset or mitigate a lack of reduction or increase in parasitic capacitance as a result of reducing gate pitch in the circuit. As gate pitch is reduced in the circuit, it may not be possible to proportionally reduce gate size without sacrificing gate control.

公开(公告)号：US20200161419A1

公开(公告)日：2020-05-21

申请号：US16196388

申请日：2018-11-20

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang

IPC: H01L29/06 ,  H01L27/092 ,  H01L23/535 ,  H01L21/764 ,  H01L21/8238

Abstract: Circuits employing an adjacent low-k dummy gate to a field-effect transistor (FET) to reduce FET source/drain parasitic capacitance, and related fabrication methods. To reduce or mitigate an increase in the source/drain parasitic capacitance(s) of a FET, a dummy gate adjacent to an active gate of the FET is provided to have a low-k (i.e., low relative permittivity). In this manner, the relative permittivity (k) between the source/drain of the FET and an adjacent dummy gate and/or source/drain of another FET is reduced, thereby reducing the parallel plate capacitance of the FET(s). Reducing parasitic capacitance of the FET(s) may allow further reduced scaling of the circuit to offset or mitigate a lack of reduction or increase in parasitic capacitance as a result of reducing gate pitch in the circuit. As gate pitch is reduced in the circuit, it may not be possible to proportionally reduce gate size without sacrificing gate control.

公开(公告)号：US10431686B1

公开(公告)日：2019-10-01

申请号：US16126886

申请日：2018-09-10

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: An integrated circuit (IC) employs a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity. A semiconductor channel structure(s) in an IC is a fin structure(s) or a gate-all-around (GAA) structure(s) employed in a Field-Effect Transistor (FET), such as a FinFET or a three-dimensional (3D) FET. The channel structures in the IC are fabricated according to a circuit cell architecture, such as a standard circuit cell (“standard cell”). The IC includes an active (e.g., diffusion) region in which a semiconductor channel structure array (e.g., semiconductor fin array) is formed according to a pattern. The IC includes a device employing a channel structure array in the active region. The channel structure array may include one active channel structure (e.g., fin) for reduced power consumption in the FinFET, and may include at least one dummy fin for increased uniformity.

公开(公告)号：US10141305B2

公开(公告)日：2018-11-27

申请号：US15266214

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Haining Yang ,  Jun Yuan ,  Kern Rim ,  Periannan Chidambaram

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L29/78

Abstract: Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.

公开(公告)号：US09978738B2

公开(公告)日：2018-05-22

申请号：US15582770

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang

IPC: H01L27/02 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.