公开(公告)号：US20170084043A1

公开(公告)日：2017-03-23

申请号：US14862532

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Shambhoo Khandelwal ,  Yang Xia ,  Xuefeng Tang ,  Jian Liang ,  Tao Wang ,  Andrew Evan Gruber ,  Eric Demers

IPC: G06T7/20 ,  G06T1/20 ,  G06T15/80 ,  G06T1/60

CPC classification number: G06T7/20 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.

公开(公告)号：US09299123B2

公开(公告)日：2016-03-29

申请号：US14160324

申请日：2014-01-21

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Andrew Evan Gruber

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: A graphics processing unit (GPU) includes an indexed streamout buffer. The indexed streamout buffer is configured to: receive vertex data of a primitive, and determine if any entries in a reuse table of the indexed streamout buffer reference the vertex data. Responsive to determining that an entry of in the reuse table references the vertex data, the buffer is further configured to: generate an index that references the vertex data, store the index in the buffer, and store a reference to the index in the reuse table. Responsive to determining that an entry does not reference the vertex data, the indexed streamout buffer is configured to: store the vertex data in the buffer, generate an index that references the vertex data, store the index in the buffer, and store a reference to the index in the reuse table.

Abstract translation: 图形处理单元（GPU）包括索引流出缓冲器。 索引的流出缓冲器被配置为：接收原语的顶点数据，并且确定索引的流出缓冲器的重用表中的任何条目是否引用顶点数据。 响应于确定所述重用表中的条目引用所述顶点数据，所述缓冲器还被配置为：生成引用所述顶点数据的索引，将所述索引存储在所述缓冲器中，并且存储对所述重用表中的所述索引的引用 。 响应于确定条目不引用顶点数据，索引流出缓冲器被配置为：将顶点数据存储在缓冲器中，生成引用顶点数据的索引，将索引存储在缓冲器中，并存储引用 重用表中的索引。

公开(公告)号：US20150089146A1

公开(公告)日：2015-03-26

申请号：US14035643

申请日：2013-09-24

Applicant: QUALCOMM Incorporated

Inventor： David A. Gotwalt ,  Thomas Edwin Frisinger ,  Andrew Evan Gruber ,  Eric Demers ,  Colin Christopher Sharp

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/08 ,  G06F2212/302 ,  G06T1/60

Abstract: The present disclosure provides for systems and methods to process a non-resident page that may include attempting to access the non-resident page, an address for the non-resident page pointing to a memory page containing default values, determining that the non-resident page should not cause a page fault based on an indicator indicating that a particular non-resident page should not generate a page fault, returning an indication that a memory read did not translate and returning the default value when the access of the non-resident page is a read and the non-resident page should not cause a page fault. Another example may discontinue a write when the access of the non-resident page is a write and the non-resident page should not cause a page fault.

Abstract translation: 本公开提供了处理非居民页面的系统和方法，其可以包括尝试访问非驻留页面，非居民页面的地址指向包含默认值的存储器页面，确定非居民页面 页面不应基于指示特定非驻留页面不应生成页面错误的指示符，返回指示，读取的存储器未翻译并在非驻留页面的访问时返回默认值 是一个读取，非驻留页面不应该导致页面错误。 当非驻留页面的访问是写入而非驻留页面不应导致页面错误时，另一个示例可能会中断写入。

公开(公告)号：US20140204080A1

公开(公告)日：2014-07-24

申请号：US14160324

申请日：2014-01-21

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Andrew Evan Gruber

IPC: G06T17/10 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: A graphics processing unit (GPU) includes an indexed streamout buffer. The indexed streamout buffer is configured to: receive vertex data of a primitive, and determine if any entries in a reuse table of the indexed streamout buffer reference the vertex data. Responsive to determining that an entry of in the reuse table references the vertex data, the buffer is further configured to: generate an index that references the vertex data, store the index in the buffer, and store a reference to the index in the reuse table. Responsive to determining that an entry does not reference the vertex data, the indexed streamout buffer is configured to: store the vertex data in the buffer, generate an index that references the vertex data, store the index in the buffer, and store a reference to the index in the reuse table.

Abstract translation: 图形处理单元（GPU）包括索引流出缓冲器。 索引的流出缓冲器被配置为：接收原语的顶点数据，并且确定索引的流出缓冲器的重用表中的任何条目是否引用顶点数据。 响应于确定所述重用表中的条目引用所述顶点数据，所述缓冲器还被配置为：生成引用所述顶点数据的索引，将所述索引存储在所述缓冲器中，并且存储对所述重用表中的所述索引的引用 。 响应于确定条目不引用顶点数据，索引流出缓冲器被配置为：将顶点数据存储在缓冲器中，生成引用顶点数据的索引，将索引存储在缓冲器中，并存储引用 重用表中的索引。

公开(公告)号：US20130265309A1

公开(公告)日：2013-10-10

申请号：US13830145

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

IPC: G06T15/80

CPC classification number: G06T15/80 ,  G06T15/00 ,  G06T15/005

Abstract: Aspects of this disclosure generally relate to a process for rendering graphics that includes performing, with a hardware shading unit of a graphics processing unit (GPU) designated for vertex shading, vertex shading operations to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit is configured to receive a single vertex as an input and generate a single vertex as an output. The process also includes performing, with the hardware shading unit of the GPU, a geometry shading operation to generate one or more new vertices based on one or more of the vertex shaded vertices, wherein the geometry shading operation operates on at least one of the one or more vertex shaded vertices to output the one or more new vertices.

Abstract translation: 本公开的方面通常涉及用于渲染图形的处理，其包括使用指定为顶点着色的图形处理单元（GPU）的硬件阴影单元执行遮蔽输入顶点的顶点着色操作，以便输出顶点着色顶点，其中 硬件单元被配置为接收单个顶点作为输入并且生成单个顶点作为输出。 该过程还包括利用GPU的硬件着色单元执行基于顶点着色顶点中的一个或多个以生成一个或多个新顶点的几何阴影操作，其中，几何阴影操作对一个 或多个顶点着色顶点，以输出一个或多个新顶点。

公开(公告)号：US12056804B2

公开(公告)日：2024-08-06

申请号：US18317825

申请日：2023-05-15

Applicant: QUALCOMM Incorporated

Inventor： Thomas Edwin Frisinger ,  Richard Hammerstone ,  Andrew Evan Gruber ,  Gang Zhong ,  Yun Du ,  Jonnala Gadda Nagendra Kumar

IPC: G06T15/00 ,  G06F9/30 ,  G06T1/20 ,  G06T1/60 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06F9/30101 ,  G06F9/30123 ,  G06T1/20 ,  G06T1/60 ,  G06T15/80

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.

公开(公告)号：US11790478B2

公开(公告)日：2023-10-17

申请号：US16984024

申请日：2020-08-03

Applicant: QUALCOMM Incorporated

Inventor： Liang Li ,  Elina Kamenetskaya ,  Andrew Evan Gruber

IPC: G06T1/20 ,  G06T15/00 ,  G06F17/14 ,  G06F9/50 ,  G06F9/30 ,  G06F17/16

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30145 ,  G06F9/5066 ,  G06F17/142 ,  G06F17/16 ,  G06T15/005

Abstract: The present disclosure relates to methods and apparatus for mapping a source location of input data for processing by a graphics processing unit. The apparatus can configure a processing element of the graphics processing unit with a predefined rule for decoding a data source parameter for executing a task by the graphics processing unit. Moreover, the apparatus can store the parameter in local storage of the processing element and configure the processing element to decode the parameter according to the at least one predefined rule to determine a source location of the input data and at least one relationship between invocations of the task. The apparatus can also load, to the local storage of the processing element, the input data from a plurality of memory addresses of the source location determined by the parameter. A one logic unit can then execute the task on the loaded input data.

公开(公告)号：US11475533B2

公开(公告)日：2022-10-18

申请号：US16877367

申请日：2020-05-18

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Yun Du

IPC: G06T15/50 ,  G06T1/60 ,  G06F9/30 ,  G06T1/20

Abstract: This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for GPR optimization in a GPU based on a GPR release mechanism. More specifically, a GPU may determine at least one unutilized branch within an executable shader based on constants defined for the executable shader. Based on the at least one unutilized branch, the GPU may further determine a number of GPRs that can be deallocated from previously allocated GPRs. The GPU may deallocate, for a subsequent thread within a draw call, the number of GPRs from the previously allocated GPRs during execution of the executable shader based on the determined number of GPRs to be deallocated.

公开(公告)号：US11373267B2

公开(公告)日：2022-06-28

申请号：US16673564

申请日：2019-11-04

Applicant: QUALCOMM Incorporated

Inventor： Tao Wang ,  Shambhoo Khandelwal ,  Andrew Evan Gruber ,  Shangmei Yu ,  Jing Gao ,  Junmei Shao ,  Thomas Edwin Frisinger ,  Rick Hammerstone

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/393

Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.

公开(公告)号：US20220068015A1

公开(公告)日：2022-03-03

申请号：US17522178

申请日：2021-11-09

Applicant: QUALCOMM Incorporated

Inventor： Vineet GOEL ,  Andrew Evan Gruber ,  Donghyun Kim

IPC: G06T15/80 ,  G06T15/00

Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.