公开(公告)号：US11467621B2

公开(公告)日：2022-10-11

申请号：US16804045

申请日：2020-02-28

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Ravi Jenkal ,  Donghyun Kim

IPC: G06F1/08 ,  G06F9/48 ,  G06F9/38 ,  G06F1/3206

Abstract: Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

公开(公告)号：US20190197651A1

公开(公告)日：2019-06-27

申请号：US15850907

申请日：2017-12-21

Applicant: QUALCOMM Incorporated

Inventor： Brendon Lewis Johnson ,  Andrew Evan Gruber ,  Jay Chunsup Yun ,  Rahul Gulati ,  Donghyun Kim ,  Alex Kwang Ho Jong

IPC: G06T1/20 ,  G06T1/60 ,  G06F11/10

CPC classification number: G06T1/20 ,  B60K35/00 ,  B60K2370/21 ,  B60R1/00 ,  B60R2300/30 ,  G06F11/1004 ,  G06T1/60 ,  G06T7/001 ,  G06T2207/30108 ,  G09G5/363 ,  G09G2330/08 ,  G09G2330/10 ,  G09G2330/12 ,  G09G2380/10 ,  G09G2380/12

Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.

公开(公告)号：US20190171538A1

公开(公告)日：2019-06-06

申请号：US15832042

申请日：2017-12-05

Applicant: QUALCOMM Incorporated

Inventor： Rahul Gulati ,  Andrew Evan Gruber ,  Brendon Lewis Johnson ,  Jay Chunsup Yun ,  Donghyun Kim ,  Alex Kwang Ho Jong ,  Anshuman Saxena

IPC: G06F11/22 ,  G06T1/20 ,  G06T15/00 ,  G06F11/07

Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

公开(公告)号：US09665975B2

公开(公告)日：2017-05-30

申请号：US14466554

申请日：2014-08-22

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Donghyun Kim ,  Gang Zhong

IPC: G06T1/00 ,  G06T15/83 ,  G06T15/00

CPC classification number: G06T15/83 ,  G06T15/005

Abstract: This disclosure describes techniques for executing shader programs in a graphics processing unit (GPU). In some examples, the techniques for executing shader programs may include executing, with a shader unit of a graphics processor, a shader program that performs vertex shader processing and that generates multiple output vertices for each input vertex that is received by the shader program. In further examples, the techniques for executing shader programs may include executing a merged vertex/geometry shader program using a non-replicated mode of execution. The non-replicated mode of execution may involve assigning each of a plurality of primitives to one merged vertex/geometry shader program instance per primitive and causing each of the instances to output a plurality of vertices. In additional examples, the techniques for executing shader programs may include techniques for selecting one of a non-replicated mode and a replicated mode for executing a merged vertex/geometry shader program.

公开(公告)号：US20130265309A1

公开(公告)日：2013-10-10

申请号：US13830145

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

IPC: G06T15/80

CPC classification number: G06T15/80 ,  G06T15/00 ,  G06T15/005

Abstract: Aspects of this disclosure generally relate to a process for rendering graphics that includes performing, with a hardware shading unit of a graphics processing unit (GPU) designated for vertex shading, vertex shading operations to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit is configured to receive a single vertex as an input and generate a single vertex as an output. The process also includes performing, with the hardware shading unit of the GPU, a geometry shading operation to generate one or more new vertices based on one or more of the vertex shaded vertices, wherein the geometry shading operation operates on at least one of the one or more vertex shaded vertices to output the one or more new vertices.

Abstract translation: 本公开的方面通常涉及用于渲染图形的处理，其包括使用指定为顶点着色的图形处理单元（GPU）的硬件阴影单元执行遮蔽输入顶点的顶点着色操作，以便输出顶点着色顶点，其中 硬件单元被配置为接收单个顶点作为输入并且生成单个顶点作为输出。 该过程还包括利用GPU的硬件着色单元执行基于顶点着色顶点中的一个或多个以生成一个或多个新顶点的几何阴影操作，其中，几何阴影操作对一个 或多个顶点着色顶点，以输出一个或多个新顶点。

公开(公告)号：US10535185B2

公开(公告)日：2020-01-14

申请号：US13830075

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

IPC: G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/50

Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

公开(公告)号：US09679347B2

公开(公告)日：2017-06-13

申请号：US14182976

申请日：2014-02-18

Applicant: QUALCOMM Incorporated

Inventor： Chunhui Mei ,  Vineet Goel ,  Donghyun Kim

IPC: G06T1/00 ,  G06T1/60 ,  G06T15/80 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/005 ,  G06T15/80

Abstract: A graphics processing unit (GPU) may allocate a shared data channel in on-chip graphics memory of the GPU that is shared by at least two stages of a graphics processing pipeline. Shader units in the GPU may execute the at least two stages of the graphics processing pipeline. The GPU may store, in the shared data channel in on-chip graphics memory, data produced by each of the at least two stages of the graphics processing pipeline executing on the shader units.

公开(公告)号：US20160055667A1

公开(公告)日：2016-02-25

申请号：US14466554

申请日：2014-08-22

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Donghyun Kim ,  Gang Zhong

IPC: G06T15/83 ,  G06T15/00

CPC classification number: G06T15/83 ,  G06T15/005

Abstract: This disclosure describes techniques for executing shader programs in a graphics processing unit (GPU). In some examples, the techniques for executing shader programs may include executing, with a shader unit of a graphics processor, a shader program that performs vertex shader processing and that generates multiple output vertices for each input vertex that is received by the shader program. In further examples, the techniques for executing shader programs may include executing a merged vertex/geometry shader program using a non-replicated mode of execution. The non-replicated mode of execution may involve assigning each of a plurality of primitives to one merged vertex/geometry shader program instance per primitive and causing each of the instances to output a plurality of vertices. In additional examples, the techniques for executing shader programs may include techniques for selecting one of a non-replicated mode and a replicated mode for executing a merged vertex/geometry shader program.

Abstract translation: 本公开描述了用于在图形处理单元（GPU）中执行着色器程序的技术。 在一些示例中，用于执行着色器程序的技术可以包括使用图形处理器的着色器单元执行着色器程序，该着色器程序执行顶点着色器处理，并且为着色器程序接收的每个输入顶点生成多个输出顶点。 在另外的示例中，用于执行着色器程序的技术可以包括使用非复制的执行模式来执行合并的顶点/几何着色器程序。 非复制的执行模式可以包括将多个基元中的每一个分配给每个基元的一个合并的顶点/几何着色器程序实例，并使每个实例输出多个顶点。 在附加示例中，用于执行着色器程序的技术可以包括用于选择非复制模式和用于执行合并顶点/几何着色器程序的复制模式之一的技术。

公开(公告)号：US12099378B2

公开(公告)日：2024-09-24

申请号：US17963129

申请日：2022-10-10

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Ravi Jenkal ,  Donghyun Kim

IPC: G06F1/08 ,  G06F1/3206 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/08 ,  G06F1/3206 ,  G06F9/3877 ,  G06F9/4837 ,  G06F9/4843

Abstract: Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

公开(公告)号：US20230118950A1

公开(公告)日：2023-04-20

申请号：US17963129

申请日：2022-10-10

Applicant: QUALCOMM Incorporated

Inventor： Edwin Jose ,  Ravi Jenkal ,  Donghyun Kim

IPC: G06F1/08 ,  G06F9/48 ,  G06F9/38 ,  G06F1/3206

Abstract: Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.