公开(公告)号：US20150294791A1

公开(公告)日：2015-10-15

申请号：US14252695

申请日：2014-04-14

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Hong Bok We ,  Young Kyu Song ,  Dong Wook Kim

IPC: H01G4/30 ,  H05K1/18 ,  H01G4/005 ,  H05K1/02 ,  H01L23/00 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/232 ,  H01G4/33 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/32265 ,  H01L2224/83801 ,  H01L2924/1205 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/10515

Abstract: A ceramic capacitor is provided that includes a first capacitor surface, a second opposing capacitor surface, and metal plates perpendicular to the first capacitor surface and second opposing capacitor surface. The metal plates extend from the first capacitor surface to the second opposing capacitor surface. The ceramic capacitor is capable of being interposed between a die and a substrate. A portion of the metal plates are capable of being coupled to conductive pads of the die on the first capacitor surface and to conductive pads of the substrate on the second capacitor surface.

Abstract translation: 提供一种陶瓷电容器，其包括第一电容器表面，第二相对电容器表面和垂直于第一电容器表面和第二相对电容器表面的金属板。 金属板从第一电容器表面延伸到第二相对的电容器表面。 陶瓷电容器能够插入在管芯和衬底之间。 金属板的一部分能够耦合到第一电容器表面上的管芯的导电焊盘和第二电容器表面上的衬底的导电焊盘。

公开(公告)号：US20240038753A1

公开(公告)日：2024-02-01

申请号：US17816502

申请日：2022-08-01

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Joan Rey Villarba Buot

IPC: H01L27/01 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L27/01 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/03 ,  H01L23/5383 ,  H01L25/0652 ,  H01L24/04 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/05073 ,  H01L2224/0231 ,  H01L2224/039 ,  H01L2224/05573 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/06138 ,  H01L24/16 ,  H01L2224/16225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L24/92 ,  H01L2224/92125

Abstract: Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.

公开(公告)号：US11817365B2

公开(公告)日：2023-11-14

申请号：US16883812

申请日：2020-05-26

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Jonghae Kim

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/3065 ,  H01L21/48 ,  H01L21/306 ,  H01L21/322

CPC classification number: H01L23/367 ,  H01L21/3065 ,  H01L21/4882 ,  H01L23/3736 ,  H01L21/30604 ,  H01L21/3221

Abstract: A semiconductor device includes a die having one or more trenches on a back side of the die. The semiconductor device also includes a layer of thermally conductive material deposited on the back side of the die to fill the one or more trenches to form one or more plated trenches. The size (e.g., surface area or thickness (Z-height)) or location of the plated trenches may be determined based on one or more heat generating elements such as logic devices (CPU or GPU, for example) on an active side of the die. The thermally conductive material, which may be a metal such as copper (Cu) or silver (Ag), has a heat dissipation coefficient that is greater than a heat dissipation coefficient of a substrate of the die.

公开(公告)号：US11776888B2

公开(公告)日：2023-10-03

申请号：US17334610

申请日：2021-05-28

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Hong Bok We ,  Chin-Kwan Kim ,  Milind Shah

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.

公开(公告)号：US11605595B2

公开(公告)日：2023-03-14

申请号：US16994398

申请日：2020-08-14

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Kuiwon Kang

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed is an apparatus and methods for making same. The apparatus includes a first insulating layer, a first metal layer disposed on a surface of the first insulating layer, and a metallization structure embedded in the first insulating layer. The metallization structure occupies only a portion of a volume of the first insulating layer. The metallization structure has a line density greater than a line density of the first metal layer.

公开(公告)号：US11594491B2

公开(公告)日：2023-02-28

申请号：US17245903

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng Weng ,  Hong Bok We

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

Abstract: Disclosed is an apparatus including a molded multi-die high density interconnect including: a bridge die having a first plurality of interconnects and second plurality of interconnects. The apparatus also includes a first die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the first plurality of interconnects of the bridge die. The apparatus also includes a second die having a first plurality of contacts and a second plurality of contacts, where the second plurality of contacts is coupled to the second plurality of interconnects of the bridge die. The coupled second plurality of contacts and interconnects have a smaller height than the first plurality of contacts of the first die and second die.

公开(公告)号：US11545425B2

公开(公告)日：2023-01-03

申请号：US17066318

申请日：2020-10-08

Applicant: QUALCOMM Incorporated

Inventor： Kun Fang ,  Jaehyun Yeon ,  Suhyung Hwang ,  Hong Bok We

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A substrate that includes a core layer, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, a plurality of first interconnects located over a surface of the at least one first dielectric layer, a plurality of second interconnects located over the surface of the at least one first dielectric layer, a plurality of third interconnects located over the surface of the at least one first dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are co-planar to the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion.

公开(公告)号：US11456291B2

公开(公告)日：2022-09-27

申请号：US16910486

申请日：2020-06-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Marcus Hsu ,  Aniket Patil

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.

公开(公告)号：US11296024B2

公开(公告)日：2022-04-05

申请号：US16875579

申请日：2020-05-15

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Jonghae Kim

IPC: H01L23/528 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

Abstract: An integrated circuit (IC) package is described. The IC package includes back-end-of-line layers on a substrate. The IC package also includes a nested interconnect structure on the back-end-of-line layers on the substrate. The nested interconnect structure is composed of an inner core pad and an outer ring pad in a concentric arrangement. The IC package further includes a redistribution layer on the nested interconnect structure. The IC package also includes an under bump metallization layer on the redistribution layer to support package balls.

公开(公告)号：US11075260B2

公开(公告)日：2021-07-27

申请号：US16176915

申请日：2018-10-31

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Chin-Kwan Kim ,  Hong Bok We ,  Jaehyun Yeon

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31

Abstract: A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.