公开(公告)号：US5228131A

公开(公告)日：1993-07-13

申请号：US666502

申请日：1991-03-06

申请人： Tatsuya Ueda ,  Toyohiko Yoshida

发明人： Tatsuya Ueda ,  Toyohiko Yoshida

IPC分类号： G06F9/38

CPC分类号： G06F9/3826 ,  G06F9/3824

摘要： The data processor related to the invention enables to designate whether the branch prediction mechanism itself should be activated or not for a conditional branch instruction, and the data processor enables to initialize branch history as required and also designates activation or inactivation of the branch prediction mechanism by setting a specific value to a specific bit of an exclusive usable register by software means. Also when a specific instruction is executed, the data processor automatically clears the branch history. As a result, in the event when the data processing efficiency is adversely declined by application of branch prediction mechanism or when monitoring external address bus, the branching prediction mechanism can be inactivated by setting the predetermined value to the exclusive usable register. Likewise, when the reliability of the branch history lowers due to such as variation in the program running condition, the data processor is capable of clearing the branch history by writing a specific value into the exclusive usable register, and when executing a specific instruction which varies the program executing condition, branch history is automatically cleared.

摘要翻译： 与本发明相关的数据处理器能够指定分支预测机制本身是否应该被激活，并且数据处理器能够根据需要初始化分支历史，并且还可以通过以下方式指定分支预测机制的激活或失活 通过软件方式将特定值设置为专用可用寄存器的特定位。 此外，当执行特定指令时，数据处理器自动清除分支历史。 结果，在通过应用分支预测机制而不利地降低数据处理效率的情况下，或者当监视外部地址总线时，可以通过将预定值设置为专用可用寄存器而使分支预测机制失效。 类似地，当分支历史的可靠性由于诸如程序运行条件的变化而降低时，数据处理器能够通过将特定值写入专用可用寄存器来清除分支历史，并且当执行改变的特定指令时 程序执行条件，分支历史记录自动清除。

公开(公告)号：US5210864A

公开(公告)日：1993-05-11

申请号：US531482

申请日：1990-05-31

申请人： Toyohiko Yoshida

发明人： Toyohiko Yoshida

IPC分类号： G06F9/30 ,  G06F11/267

CPC分类号： G06F11/2236 ,  G06F9/30

摘要： A microprocessor which incorporates a processor mode using processor instructions for executing pipeline processing of instructions and a test mode using test instructions for easily diagnosing internal function blocks by allowing them to independently operate, and transfers the operation mode to the test mode with holding contents of a plurality of internal registers by test interruption during executing instructions under the processor mode, and then transfers the operation mode to the processor mode with holding the content of the plurality of internal registers by executing a dedicated instruction under the test mode, so that diagnosis of respective function blocks is executed by the test program which reciprocates both modes using the processor instruction and the test instruction.

摘要翻译： 一种使用处理器模式的微处理器，其使用用于执行指令的流水线处理的处理器指令和使用测试指令的测试模式，用于通过允许它们独立地操作来容易地诊断内部功能块，并且将操作模式转移到测试模式， 通过在处理器模式下执行指令期间的测试中断来执行多个内部寄存器，然后通过在测试模式下执行专用指令来保持多个内部寄存器的内容，从而将操作模式转移到处理器模式，从而使各个 功能块由使用处理器指令和测试指令使两种模式往复的测试程序执行。

公开(公告)号：US5148529A

公开(公告)日：1992-09-15

申请号：US312104

申请日：1989-02-17

申请人： Tatsuya Ueda ,  Toyohiko Yoshida

发明人： Tatsuya Ueda ,  Toyohiko Yoshida

IPC分类号： G06F9/38

CPC分类号： G06F9/3826 ,  G06F9/30181 ,  G06F9/3844

摘要： A pipelined multi-stage data processor has a bypass circuit which is enabled when a memory reading request signal from the operand fetch stage and a memory writing request signal from the execution stage are simultaneously received by a control device with respect to an identical location in the memory. The bypass circuit operates to cause the write data to be written into the memory to be directly transferred to the fetch stage so that the memory reading operation is performed without actually accessing the memory.

摘要翻译： 流水线式多级数据处理器具有旁路电路，当来自操作数获取级的存储器读取请求信号和来自执行级的存储器写入请求信号被控制装置相对于相同位置同时接收时，该电路被使能 记忆。 旁路电路用于使写入数据被写入存储器以直接传送到读取级，使得在不实际访问存储器的情况下执行存储器读取操作。

公开(公告)号：US4907147A

公开(公告)日：1990-03-06

申请号：US156271

申请日：1988-02-12

申请人： Yuuichi Saito ,  Toyohiko Yoshida

发明人： Yuuichi Saito ,  Toyohiko Yoshida

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3824 ,  G06F9/3838

摘要： A system for preventing register conflict in a pipeline including a flag group memories at selected stages for storing flag groups indicating which general purpose registers are reserved by the instructions being processed at the selected stages. A flag group associated with a particular instruction is shifted with the instruction through the pipeline.

摘要翻译： 一种用于防止流水线中的寄存器冲突的系统，包括在选定阶段的标志组存储器，用于存储指示哪些通用寄存器由在所选阶段处理的指令预留的标志组。 与特定指令相关联的标志组通过管线与指令一起移位。

公开(公告)号：US4802112A

公开(公告)日：1989-01-31

申请号：US924565

申请日：1986-10-28

申请人： Toyohiko Yoshida ,  Tatsuya Ueda

发明人： Toyohiko Yoshida ,  Tatsuya Ueda

IPC分类号： G06F7/50 ,  G06F7/503 ,  G06F7/506 ,  G06F7/508

CPC分类号： G06F7/503

摘要： When a carry signal generated in an n-th bit is propagated to an (n+1)th bit, two n-MOS transistors (12.sub.n+1 and 13.sub.n+1) connected by a signal line (C.sub.n) are turned on to prompt transition of the signal line (C.sub.n) to a zero potential, thereby to increase the speed for propagating the carry signal. When the signal line (C.sub.n) propagates no carry signal, a p-MOS transistor (11.sub.n+1) is turned on to pull up the signal line (C.sub.n) to a supply potential V.sub.CC, thereby to stabilize the potential thereof.

摘要翻译： 当第n位产生的进位信号传播到第（n + 1）位时，由信号线（Cn）连接的两个n-MOS晶体管（12n + 1和13n + 1）导通，以提示 信号线（Cn）的转变为零电位，从而增加用于传播进位信号的速度。 当信号线（Cn）不传送进位信号时，p-MOS晶体管（11n + 1）导通，将信号线（Cn）上拉到电源电位VCC，从而稳定其电位。

公开(公告)号：US20080133887A1

公开(公告)日：2008-06-05

申请号：US11987704

申请日：2007-12-04

申请人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

发明人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

IPC分类号： G06F9/38

CPC分类号： G06F9/3814 ,  G06F7/5443 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3822 ,  G06F9/3875

摘要： When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

公开(公告)号：US06851045B2

公开(公告)日：2005-02-01

申请号：US09116260

申请日：1998-07-16

申请人： Edgar Holmann ,  Toyohiko Yoshida

发明人： Edgar Holmann ,  Toyohiko Yoshida

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F13/00

CPC分类号： G06F9/30192 ,  G06F9/30058 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3842

摘要： A microprocessor including an instruction decoder for decoding a branch instruction to output a decoded result, a program counter, and a program counter controller for controlling the program counter on the basis of the decoded result. The program counter controller includes a first register for storing a first program counter value output from the instruction decoder. The program counter controller detects a coincidence of the first program counter value stored in the first register with a value of the program counter to set a second program counter value indicating a branch target of the branch instruction into the program counter.

摘要翻译： 一种微处理器，包括用于解码分支指令以输出解码结果的指令解码器，程序计数器和用于根据解码结果控制程序计数器的程序计数器控制器。 程序计数器控制器包括用于存储从指令译码器输出的第一程序计数值的第一寄存器。 程序计数器控制器检测存储在第一寄存器中的第一程序计数器值与程序计数器的值的一致，以将指示转移指令的分支目标的第二程序计数器值设置到程序计数器中。

公开(公告)号：US06792045B2

公开(公告)日：2004-09-14

申请号：US09769415

申请日：2001-01-26

申请人： Tetsuya Matsumura ,  Toyohiko Yoshida

发明人： Tetsuya Matsumura ,  Toyohiko Yoshida

IPC分类号： H04N712

CPC分类号： H04N19/40

摘要： An MPEG2 decoder portion decodes an input bit stream and outputs a digital decoded image while extracting coding information and supplying the same to a control portion. An MPEG2 encoder portion re-encodes the digital decoded image output from the MPEG2 decoder portion. Coding information supplied from the control portion is reflected on a coding parameter in re-encoding. Transcoding between the MPEG2 standard and the DV standard can also be executed by arranging a decoder or an encoder corresponding to the DV standard in place of either the MPEG2 decoder portion or the MPEG2 encoder portion.

摘要翻译： MPEG2解码器部分解码输入比特流并输出数字解码图像，同时提取编码信息并将其提供给控制部分。 MPEG2编码器部分对从MPEG2解码器部分输出的数字解码图像进行重新编码。 从重新编码的反编码参数反映从控制部分提供的编码信息。 MPEG2标准和DV标准之间的转码也可以通过布置与DV标准相对应的解码器或编码器代替MPEG2解码器部分或MPEG2编码器部分来执行。

公开(公告)号：US06687299B2

公开(公告)日：2004-02-03

申请号：US09261171

申请日：1999-03-03

申请人： Toyohiko Yoshida ,  Kazuya Ishihara ,  Yoshinori Matsuura ,  Tetsuya Matsumura ,  Vasily Moshnyaga

发明人： Toyohiko Yoshida ,  Kazuya Ishihara ,  Yoshinori Matsuura ,  Tetsuya Matsumura ,  Vasily Moshnyaga

IPC分类号： H04B166

CPC分类号： H04N5/145 ,  G06T7/238 ,  G06T2207/10016 ,  H04N19/51 ,  H04N19/557

摘要： A motion estimation method capable of setting an optimum threshold value and allowing high speed processing includes the steps of: sequentially selecting one of blocks to be searched from a search range; sequentially calculating a difference between corresponding sample values of a reference block and one of blocks to be searched and accumulating an absolute value of difference; comparing an intermediate result of an accumulation value and a prescribed threshold value for a prescribed number of samples and interrupting the step of accumulating the absolute value of difference when the intermediate result exceeds the prescribed threshold value; and making one of blocks to be searched having a minimum final result of the accumulation value correspond to the reference block. The prescribed threshold value is dependent on the reference block. It is noted that the motion estimation apparatus is also disclosed.

摘要翻译： 能够设定最佳阈值并允许高速处理的运动估计方法包括以下步骤：从搜索范围顺序选择要搜索的块之一; 顺序地计算参考块的对应样本值与要搜索的块中的一个的差值，并累加差值的绝对值; 比较规定数量样本的累积值和规定阈值的中间结果，并且当中间结果超过规定阈值时中断累积差分绝对值的步骤; 并且使具有累积值的最小最终结果的要搜索的块之一对应于参考块。 规定的阈值取决于参考块。 注意，还公开了运动估计装置。

公开(公告)号：US06016543A

公开(公告)日：2000-01-18

申请号：US942295

申请日：1997-10-01

申请人： Kazumasa Suzuki ,  Atsushi Mohri ,  Akira Yamada ,  Toyohiko Yoshida

发明人： Kazumasa Suzuki ,  Atsushi Mohri ,  Akira Yamada ,  Toyohiko Yoshida

IPC分类号： G06F9/38 ,  G06F11/14

CPC分类号： G06F9/30167 ,  G06F9/30072 ,  G06F9/3826 ,  G06F9/3842 ,  G06F9/3885

摘要： In a microprocessor having conditional execution instructions, an execution halt circuit incorporated in an instruction decoder temporarily halts the execution of a current instruction according to the operation result of a preceding instruction in a program. When a conditional execution decision circuit judges to cancel the execution of the preceding instruction, the conditional execution decision circuit cancels a start signal indicating to initiate the operation of the preceding instruction. Furthermore, the conditional execution decision section or circuit judges whether a conditional data stored in a general purpose flag is equal to a condition stored in an execution conditional field, and bypass control sections control use of bypasses and data passes for data transfer operation according to the decision result of the conditional execution decision section.

摘要翻译： 在具有条件执行指令的微处理器中，结合在指令解码器中的执行停止电路根据程序中的前一指令的操作结果临时停止当前指令的执行。 当条件执行判定电路判断取消前一指令的执行时，条件执行判定电路取消指示开始前一指令的动作的开始信号。 此外，条件执行决定部分或电路判断存储在通用标志中的条件数据是否等于存储在执行条件字段中的条件，并且旁路控制部分根据控制部分控制旁路和数据通过用于数据传送操作 条件执行决定部分的决策结果。