公开(公告)号：US20230369289A1

公开(公告)日：2023-11-16

申请号：US17742799

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Jong-Ru Guo ,  Zhen Zhou ,  Jason Mix ,  Chia-Pin Chiu ,  Zuoguo Wu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49838 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06548

Abstract: Embodiments of a microelectronic assembly comprise a package substrate, a first integrated circuit (IC) die, a second IC die between the first IC die and the package substrate, a dielectric material between the first IC die and the package substrate, and a plurality of vias through the dielectric material, the vias coupling the first IC die and the package substrate. The microelectronic assembly is in a space defined by three mutually orthogonal axes, a first axis, a second axis and a third axis; the package substrate, the first IC die and the second IC die are mutually parallel in first planes defined by the first axis and the third axis; the vias are in one or more second planes defined by the second axis and the third axis; and the vias are inclined at an angle not equal to ninety degrees around the first axis.

公开(公告)号：US11810884B2

公开(公告)日：2023-11-07

申请号：US17570255

申请日：2022-01-06

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L24/25 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L21/568 ,  H01L23/3128 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/255 ,  H01L2224/2512 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US11581671B2

公开(公告)日：2023-02-14

申请号：US16361537

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Steven A. Klein ,  Chia-Pin Chiu ,  Shankar Devasenathipathy

IPC: H01R13/62 ,  H01R12/70 ,  H01R13/50 ,  H01R13/24 ,  H01R12/71

Abstract: An integrated circuit (IC) socket comprising a housing with a land side, an opposing die side, and sidewalls around a perimeter of the housing. The housing comprises a first dielectric. A plurality of socket pins extends from the land side of the housing through socket pin holes in the housing over the die side of the housing. A second dielectric is within the interstitial regions between the socket pins and sidewalls of the socket pin holes. A frame structure extends around at least a portion of the perimeter of the housing, and a mesh structure is embedded within the first dielectric. The mesh structure has plurality of mesh filaments extending between the plurality of socket pin holes and coupled to the frame structure.

公开(公告)号：US11444003B2

公开(公告)日：2022-09-13

申请号：US16144584

申请日：2018-09-27

Applicant: INTEL CORPORATION

Inventor： Zhimin Wan ,  Chia-Pin Chiu ,  Chandra Mohan Jha ,  Weihua Tang ,  Shankar Devasenathipathy

IPC: H01L23/473 ,  H01L25/18 ,  H01L23/467 ,  H01L23/367 ,  H01L23/373

Abstract: An integrated heat spreader includes channel structures assembled in a frame. Each channel structure is independent of the other, and can be used to dissipate heat from integrated circuitry at a specific location within a package, and without allowing heat from that particular location to propagate to integrated circuitry at other locations within the package. Each channel structure can be implemented with metal having a high thermal conductivity (e.g., copper). The channel structures can be used in conjunction with liquid-based cooling or air-based cooling. The frame can be implemented with low thermal conductivity molding compound or plastic so the heat transfer from one channel structure to another is inhibited. The channel structures can have different configurations (e.g., straight, pillars, and/or pin fins) to provide different rates of flow, mixing, and/or cooling. The flow direction of air or liquid for the channel structures can be the same (parallel) or different (counter).

公开(公告)号：US11251150B2

公开(公告)日：2022-02-15

申请号：US17077996

申请日：2020-10-22

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L21/56

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US10923429B2

公开(公告)日：2021-02-16

申请号：US16940024

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20200073099A1

公开(公告)日：2020-03-05

申请号：US16336607

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Anna M. Prakash ,  Amanuel M. Abebaw ,  Olga Gorbounova ,  Ching-Ping Janet Shen ,  Shan Zhong ,  Mark Saltas

IPC: G02B19/00 ,  G01J1/04

Abstract: Various embodiments disclosed relate to an assembly. The assembly includes a compound parabolic concentrator including an exit aperture that has a generally circular perimeter, which defines a circumference of the exit aperture. The assembly further includes a photodiode sensor generally that is aligned with the exit aperture of the compound parabolic concentrator. An optical adhesave layer adheres the exit aperture of the compound parabolic concentrator to the photodiode sensor. A protrusion extends between at least a portion of the perimeter of the compound parabolic concentrator exit aperture and the photodiode.

公开(公告)号：US10438915B2

公开(公告)日：2019-10-08

申请号：US16239670

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L21/56

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US10366951B2

公开(公告)日：2019-07-30

申请号：US15620555

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20180350737A1

公开(公告)日：2018-12-06

申请号：US16002740

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.