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    Hybrid CMOS nanowire mesh device and PDSOI device
    61.
    发明授权
    Hybrid CMOS nanowire mesh device and PDSOI device 有权
    混合CMOS纳米线网格装置和PDSOI装置

    公开(公告)号：US09053981B2

    公开(公告)日：2015-06-09

    申请号：US14194766

    申请日：2014-03-02

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Leland Chang ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC: H01L27/12 ,  H01L21/28 ,  H01L29/78 ,  H01L27/088 ,  H01L21/84 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786

    CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/28 ,  H01L21/845 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

    Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer.

    Abstract translation: SOI衬底上的半导体混合结构。 SOI衬底的第一部分包含纳米线网状器件，并且SOI衬底的第二部分包含部分耗尽的绝缘体上半导体（PDSOI）器件。 纳米线网状器件包括位于SOI衬底上的层叠且间隔开的半导体纳米线，每个半导体纳米线具有两个端部段，其中一个端部段连接到源极区域，另一个端部段连接到漏极区域。 纳米线网状器件还包括在层叠和间隔开的半导体纳米线的至少一部分上的栅极区域。 PDSOI器件包括在衬底上的部分耗尽的半导体层，以及在部分耗尽的半导体层的至少一部分上的栅极区域。

    Diode structure and method for wire-last nanomesh technologies
    62.
    发明授权
    Diode structure and method for wire-last nanomesh technologies 有权
    最后纳米技术的二极管结构和方法

    公开(公告)号：US09006087B2

    公开(公告)日：2015-04-14

    申请号：US13761476

    申请日：2013-02-07

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  B82Y99/00

    CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L27/0629 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66136 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696 ,  H01L29/861 ,  Y10S977/762 ,  Y10S977/938

    Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.

    Abstract translation: 一方面，一种制造电子设备的方法包括以下步骤。 在SOI晶片上的堆叠中形成交替的器件和牺牲层系列。 将纳米线棒蚀刻到器件/牺牲层中，使得堆叠的第一部分中的每个器件层和堆叠的第二部分中的每个器件层具有源极区，漏极区和多个纳米线 通道连接源极区域和漏极区域。 从纳米线条之间移除牺牲层。 选择性地形成围绕堆叠的第一部分中的纳米线通道的共形栅极介电层，其用作纳米级FET晶体管的沟道区。 在堆叠的第一和第二部分中围绕纳米线通道形成栅极。

    Embedded silicon germanium N-type field effect transistor for reduced floating body effect
    63.
    发明授权
    Embedded silicon germanium N-type field effect transistor for reduced floating body effect 有权
    嵌入式硅锗N型场效应晶体管，可减少浮体效应

    公开(公告)号：US08969964B2

    公开(公告)日：2015-03-03

    申请号：US14049736

    申请日：2013-10-09

    Applicant: International Business Machines Corporation

    Inventor： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238

    CPC classification number: H01L27/1203 ,  H01L21/8238 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78621

    Abstract: A semiconductor device includes a gate stack formed on an active region in a p-type field effect transistor (pFET) portion of a silicon-on-insulator (SOI) substrate. The SOI substrate includes a n-type field effect transistor (nFET) portion. A gate spacer is formed over the gate stack. A source region and a drain region are formed within a first region and a second region, respectively, of the pFET portion of the semiconductor layer including embedded silicon germanium (eSiGe). A source region and a drain region are formed within a first region and a second region, respectively, of the nFET portion of the semiconductor layer including eSiGe. The source and drain regions within the pFET portion includes at least one dimension that is different from at least one dimension of the source and drain regions within the nFET portion.

    Abstract translation: 半导体器件包括形成在绝缘体上硅（SOI））衬底的p型场效应晶体管（pFET）部分中的有源区上的栅叠层。 SOI衬底包括n型场效应晶体管（nFET）部分。 在栅极堆叠上形成栅极间隔物。 源极区域和漏极区域分别形成在包括嵌入硅锗（eSiGe）的半导体层的pFET部分的第一区域和第二区域内。 源区域和漏极区域分别形成在包括eSiGe的半导体层的nFET部分的第一区域和第二区域内。 pFET部分内的源极区和漏极区包括与nFET部分内的源极和漏极区的至少一个维度不同的至少一个维度。

    Embedded silicon germanium N-type filed effect transistor for reduced floating body effect
    64.
    发明授权
    Embedded silicon germanium N-type filed effect transistor for reduced floating body effect 有权
    嵌入式硅锗N型场效应晶体管，可减少浮体效应

    公开(公告)号：US08940591B2

    公开(公告)日：2015-01-27

    申请号：US14049765

    申请日：2013-10-09

    Applicant: International Business Machines Corporation

    Inventor： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC: H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238

    CPC classification number: H01L27/1203 ,  H01L21/8238 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78621

    Abstract: A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.

    Abstract translation: 一种用于制造半导体器件的方法包括在绝缘体上硅衬底的有源区上形成栅叠层。 有源区在半导体层内并掺杂有p型掺杂剂。 围绕栅极堆叠形成栅极间隔物。 在为源极区域保留的区域中形成第一沟槽，并且在为漏极区域保留的区域中形成第二沟槽。 形成第一和第二沟槽，同时保持暴露为源极区域保留的区域和为漏极区域保留的区域。 硅锗外延生长在第一沟槽和第二沟槽内，同时保持分别保留用于源区和漏区的区域。

    FINFET WITH VERTICAL SILICIDE STRUCTURE
    65.
    发明申请
    FINFET WITH VERTICAL SILICIDE STRUCTURE 审中-公开
    FINFET与垂直硅胶结构

    公开(公告)号：US20140339640A1

    公开(公告)日：2014-11-20

    申请号：US14452758

    申请日：2014-08-06

    Applicant: International Business Machines Corporation

    Inventor： Veeraraghavan S. Basker ,  Chung-Hsun Lin ,  Tenko Yamashita ,  Chun-Chen Yeh

    IPC: H01L27/12 ,  H01L29/06 ,  H01L29/45 ,  H01L29/417

    CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

    Abstract: FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls.

    Abstract translation: FinFET和用于制造具有垂直硅化物结构的FinFET的方法。 一种方法包括提供具有多个翅片的基板，在基板上形成栅极堆叠，其中栅极堆叠具有至少一个侧壁并形成邻近栅极堆叠侧壁的偏置间隔物。 该方法还包括生长外延膜，其将翅片合并以形成外延合并层，形成与偏置间隔物的至少一部分相邻的场氧化物层，并去除场氧化物层的一部分以暴露部分 的外延合并层。 该方法还包括去除外延合并层的暴露部分的至少一部分以形成外延合并侧壁和外延合并间隔区，并在外延合并侧壁内形成硅化物以形成硅化物层和二 硅化物侧壁

    APPARATUS FOR MODELING OF FINFET WIDTH QUANTIZATION
    68.
    发明申请
    APPARATUS FOR MODELING OF FINFET WIDTH QUANTIZATION 有权
    FINFET宽度量化建模设备

    公开(公告)号：US20140201700A1

    公开(公告)日：2014-07-17

    申请号：US13970806

    申请日：2013-08-20

    Applicant: International Business Machines Corporation

    Inventor： Wilfried Ernest-August HAENSCH ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Hailing Wang ,  Richard Q. Williams

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/5009 ,  G06F17/5036

    Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.

    Abstract translation: 描述了一种用于对FinFET宽度量化进行建模的方法。 该方法包括将FinFET器件的FinFET模型拟合到单个鳍电流/电压特性。 FinFET器件包括多个翅片。 该方法包括获得至少一个样本FinFET器件的统计数据。 统计数据包括DIBL数据和SS数据。 该方法还包括使用DIBL数据和SS数据将FinFET模型拟合到电流变化以关闭统计数据中的finFET器件（IOFF），并且确定用于关断finFET器件（VOFF）的电压模型 ）。 该方法还包括将FinFET模型拟合到VOFF。

    Semiconductor device having silicon on stressed liner (SOL)
    70.
    发明授权
    Semiconductor device having silicon on stressed liner (SOL) 有权
    在应力衬垫（SOL）上具有硅的半导体器件

    公开(公告)号：US08664058B2

    公开(公告)日：2014-03-04

    申请号：US13765830

    申请日：2013-02-13

    Applicant: International Business Machines Corporation

    Inventor： Stephen W. Bedell ,  Josephine B. Chang ,  Chung-Hsun Lin

    IPC: H01L21/8238

    CPC classification number: H01L29/66477 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7849

    Abstract: A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.

    Abstract translation: 公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。 在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。 该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。 该半导体层将晶体管与应力衬垫分开。 在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。 在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。 端盖可以形成在应力衬垫的端部处的凹部中。

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