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104 条记录 (耗时 0.021 秒)

    Transistor arrangement, integrated circuit and method for operating field effect transistors
    61.
    发明授权
    Transistor arrangement, integrated circuit and method for operating field effect transistors 有权
    晶体管布置，集成电路和操作场效应晶体管的方法

    公开(公告)号：US07733156B2

    公开(公告)日：2010-06-08

    申请号：US10570924

    申请日：2004-09-01

    申请人： Ralf Brederlow ,  Jeongwook Koh ,  Roland Thewes

    发明人： Ralf Brederlow ,  Jeongwook Koh ,  Roland Thewes

    IPC分类号： H03K17/16 ,  H03K17/687

    CPC分类号： H03F3/211 ,  H01L2924/0002 ,  H03F1/26 ,  H03F3/72 ,  H03F2203/21178 ,  H03F2203/7215 ,  H01L2924/00

    摘要： The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

    摘要翻译： 晶体管装置包括第一和第二场效应晶体管，其包括第一和第二源极漏极连接以及用于施加第一或第二信号的控制连接。 两个场效应晶体管具有相同的导电类型。 晶体管布置被配置为使得第一信号可以以交替方式施加到第一场效应晶体管的控制连接，并且第二信号可以以与第二场效应的控制连接同时的方式施加 晶体管和/或第二信号可以被施加到第一场效应晶体管的控制连接，并且第一信号可以同时施加到第二场效应晶体管的控制连接。

    Potentiostatic circuit arrangement on a biosensor for digitisation of the measured current
    62.
    发明申请
    Potentiostatic circuit arrangement on a biosensor for digitisation of the measured current 有权
    用于数字化测量电流的生物传感器上的静电电路布置

    公开(公告)号：US20070080060A1

    公开(公告)日：2007-04-12

    申请号：US10556731

    申请日：2004-05-11

    申请人： Alexander Frey ,  Chirstian Paulus ,  Meinrad Schienle ,  Roland Thewes

    发明人： Alexander Frey ,  Chirstian Paulus ,  Meinrad Schienle ,  Roland Thewes

    IPC分类号： G01N33/487 ,  G01N27/26

    CPC分类号： G01R19/252 ,  C12Q1/6825 ,  G01N27/3276

    摘要： A circuit arrangement, an electrochemical sensor, a sensor arrangement, and a method for processing a current signal provided by a sensor electrode are disclosed. The circuit arrangement includes a sensor electrode, a first circuit unit, electrically coupled to the sensor electrode and a second circuit unit, including a first capacitor, whereby the first circuit arrangement is embodied to hold the electrical potential of the sensor electrode in a given first reference range about a set electrical potential and, when the sensor electrode potential falls outside the first reference range, the first capacitor and the sensor electrode are coupled such that a matching of the electrical potentials is possible. The second circuit unit is embodied such that, when the electrical potential of the first capacitor falls outside a second reference range, this event is detected and the first capacitor brought to a first electrical reference potential.

    摘要翻译： 公开了电路装置，电化学传感器，传感器装置和用于处理由传感器电极提供的电流信号的方法。 电路装置包括传感器电极，电耦合到传感器电极的第一电路单元和包括第一电容器的第二电路单元，由此第一电路装置被实施为将传感器电极的电势保持在给定的第一 参考范围关于设定的电位，并且当传感器电极电位落在第一参考范围之外时，第一电容器和传感器电极被耦合，使得电位的匹配是可能的。 实施第二电路单元，使得当第一电容器的电位落在第二参考范围之外时，检测到该事件，并将第一电容器带到第一电参考电位。

    Circuit configuration and method for assessing capacitances in matrices
    64.
    发明授权
    Circuit configuration and method for assessing capacitances in matrices 失效
    用于评估矩阵中的电容的电路配置和方法

    公开(公告)号：US06870373B2

    公开(公告)日：2005-03-22

    申请号：US10236889

    申请日：2002-09-06

    申请人： Ute Kollmer ,  Stephan Sauter ,  Carsten Linnenbank ,  Roland Thewes

    发明人： Ute Kollmer ,  Stephan Sauter ,  Carsten Linnenbank ,  Roland Thewes

    IPC分类号： G11C7/06 ,  G11C11/405 ,  G11C11/4091 ,  G01R31/11 ,  G01R27/26

    CPC分类号： G11C7/06 ,  G11C11/405 ,  G11C11/4091 ,  G11C2207/063

    摘要： A circuit configuration for assessing capacitances in a matrix, which has a number of rows with at least one capacitance in at least one dimension, includes a test arm connected to first electrodes of each of the capacitances to be assessed and by which two different potentials can be applied to the first electrodes, a measurement arm connected to second electrodes of each of the capacitances to be assessed and that has a first measurement path and a second measurement path connected to a common potential. The first measurement path has an instrument for assessing the capacitances and the first and second measurement paths can be connected to the second electrodes. The circuit configuration has a drive device that connects each of the capacitances to be assessed individually to the two different potentials.

    摘要翻译： 用于评估在至少一维中具有至少一个电容的行数的矩阵中的电容的电路配置包括连接到要评估的每个电容的第一电极的测试臂，并且两个不同的电位可以被 施加到第一电极，测量臂连接到要评估的每个电容的第二电极，并且具有连接到公共电位的第一测量路径和第二测量路径。 第一测量路径具有用于评估电容的仪器，并且第一和第二测量路径可以连接到第二电极。 电路配置具有驱动装置，其将要被分别评估的每个电容连接到两个不同的电位。

    Magnetoresistive memory and method for reading a magnetoresistive memory
    65.
    发明授权
    Magnetoresistive memory and method for reading a magnetoresistive memory 失效
    磁阻存储器和读取磁阻存储器的方法

    公开(公告)号：US06842363B2

    公开(公告)日：2005-01-11

    申请号：US10455154

    申请日：2003-06-05

    申请人： Roland Thewes ,  Werner Weber ,  Hugo Van Den Berg

    发明人： Roland Thewes ,  Werner Weber ,  Hugo Van Den Berg

    IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L43/08 ,  G11C11/00

    CPC分类号： G11C11/15 ,  G11C11/16

    摘要： A magnetoresistive memory includes a control circuit with a first pole that, via a reading distributor, can be individually connected to first ends of bit lines by switching elements. The control circuit also has a second pole, which supplies power to an evaluator, and has a third pole that is connected to a reference voltage source. The readout circuit additionally includes a third voltage source having a voltage, which is approximately equal to the voltage of the first reading voltage source and which can be individually connected to second ends of the bit lines by means of switching elements. Finally, the readout circuit includes a fourth voltage source, which can be individually connected to second ends of the word lines by means of switching elements.

    摘要翻译： 磁阻存储器包括具有第一极的控制电路，其经由读取分配器可以通过开关元件单独地连接到位线的第一端。 控制电路还具有向评估器供电的第二极，并且具有连接到参考电压源的第三极。 读出电路还包括具有大致等于第一读取电压源的电压并且可以通过开关元件单独地连接到位线的第二端的电压的第三电压源。 最后，读出电路包括第四电压源，其可以通过开关元件单独地连接到字线的第二端。

    Circuit configuration for evaluating the information content of a memory cell
    66.
    发明授权
    Circuit configuration for evaluating the information content of a memory cell 有权

    公开(公告)号：US06525978B2

    公开(公告)日：2003-02-25

    申请号：US10113417

    申请日：2002-04-01

    申请人： Werner Weber ,  Roland Thewes

    发明人： Werner Weber ,  Roland Thewes

    IPC分类号： G11C702

    CPC分类号： G11C11/16 ,  G11C11/1673

    摘要： A description is given of a method and a circuit configuration for evaluating an information content of a memory cell, preferably of an MRAM memory cell, or of a memory cell array. In order to be able to perform accurate and reliable evaluation of the memory cell, a first current value flowing through the memory cell or a voltage value correlated with the current value is measured and conducted through a first circuit branch, which has a switch and a capacitance, and is buffer-stored. The memory cell is subsequently subjected to a programming operation. Afterward, in the same memory cell a second current value or voltage value is measured and conducted through a second circuit branch that has a switch and a capacitance and is buffer-stored there. The two measured values are compared with one another in an evaluation unit.

    Device for evaluating cell resistances in a magnetoresistive memory
    67.
    发明授权
    Device for evaluating cell resistances in a magnetoresistive memory 有权

    公开(公告)号：US06512688B2

    公开(公告)日：2003-01-28

    申请号：US09968287

    申请日：2001-10-01

    申请人： Roland Thewes ,  Werner Weber

    发明人： Roland Thewes ,  Werner Weber

    IPC分类号： G11C1100

    CPC分类号： G11C11/15 ,  G11C11/14 ,  G11C11/16

    摘要： A magneto resistive memory contains first switches, a word line voltage source generating a word line voltage connected to the first switches, a line node, second switches, and cells formed of cell resistors each having a first terminal connected to the word line voltage through one of the first switches and a second terminal connected to the line node through one of the second switches. A reference resistor is connected to the line node and a reference voltage source is connected to the reference resistor. The reference resistor with the reference voltage source brings about a reduction in a respective cell current, flowing from the line node, by an average current. A device is connected to the line node and evaluates the cell resistors. The device has an amplifier for converting a difference between the respective cell current and the average current into a voltage functioning as an evaluation signal.

    Magnetoresistive memory having elevated interference immunity
    68.
    发明授权
    Magnetoresistive memory having elevated interference immunity 有权
    具有提高抗干扰能力的磁阻记忆体

    公开(公告)号：US06366494B2

    公开(公告)日：2002-04-02

    申请号：US09821964

    申请日：2001-03-30

    申请人： Werner Weber ,  Roland Thewes ,  Gunther Plasa

    发明人： Werner Weber ,  Roland Thewes ,  Gunther Plasa

    IPC分类号： G11C1115

    CPC分类号： G11C11/16 ,  H01L27/222

    摘要： The magnetoresistive memory provides for an improvement in interference immunity even though only a small chip area is used. Word lines are situated vertically between two complementary bit lines, a magnetoresistive memory system of a regular location is situated between a bit line and a word line, and an appertaining magnetoresistive layer system of a complementary memory location is situated between the complementary bit line and the word line in the vertical direction.

    摘要翻译： 即使仅使用小的芯片面积，磁阻存储器也提供了抗干扰性的改善。 字线垂直位于两个互补位线之间，规则位置的磁阻存储器系统位于位线和字线之间，并且互补存储器位置的相应磁阻层系统位于互补位线和 字线在垂直方向。